Professor Krishna V. Palem, Rice University
Abstract
Professor Krishna V. Palem is the Kenneth and Audrey Kennedy Professor of Computing at the Department of Computer Science at the George Brown School of Engineering at Rice University. His research interests while focussed on all aspects of embedded computing, include adaptive architectures and computing, algorithms, compiler optimizations, embedded systems, low energy computing and nanoelectronics. He is the founding director of VISEN center at Rice University.
Reliability of on-chip systems in 22nm technology and beyond is becoming the major design constraint. Significant efforts at device and circuit level have been undertaken to cope with the problem. Recent designs and research investigations show that pure hardware-driven approaches will not only turn out to be costly but are also ineffective. We believe that the key to reliable hardware/software on-chip systems is in exploiting cross-layer approaches between software and hardware. In particular, we propose reliability-enhancing compilation techniques that take the hardware's susceptibility against various kinds of errors into account and that generate code that is less likely to lead to errors on potentially unreliable hardware. The talk gives an overview of compilations techniques and resiliency modeling approaches currently under investigation in our lab.
Professor Jorg Henkel is currently with Karlsruhe Institute of Technology (KIT), Germany, where he is directing the Chair for Embedded Systems CES. Before, he was with NEC Laboratories in Princeton, NJ. His current research is focused on design and architectures for embedded systems with focus on reliability and low power. Prof. Henkel was Program Chair of CODES'01, RSP'02, ISLPED'06, SIPS'08 and CASES'09, Estimedia'11, VLSI Design'12, ICCAD'12 and served as General Chair for CODES'02, ISLPED'09 and Estimedia'12. He is/has been a steering committee member of major conferences in the embedded systems field like at ICCAD, ISLPED, CODES+ISSS, CASES and is/has been an editorial board member of various journals like the IEEE TVLSI, IEEE TCAD, JOLPE etc. He received the 2008 DATE Best Paper Award, the 2009 IEEE/ACM William J. Mc Calla ICCAD Best Paper Award, the CODES+ISSS 2011 Best Paper Award and the MaXentric Technologies AHS 2011 Best Paper Award. His students have won various awards including the EDAA PhD Award. He is the Chairman of the IEEE Computer Society, Germany Section, and the Editor-in-Chief of the ACM Transactions on Embedded Computing Systems (ACM TECS). He is an initiator and the coordinator of the German Research Foundation's (DFG) program on 'Dependable Embedded Systems' (SPP 1500) and the site coordinator (of the Karlsruhe site) of the three-university Transregional Collaborative Research Center (DFG TR 89) on "Invasive Computing". Prof. Henkel is also an elected board member (i.e. `Fachkollegiat') of the German Research Foundation's (DFG) Board on Technical Computer Science. He holds ten US patents.
Reducing device dimensions, increasing transistor densities, and smaller timing windows, expose the vulnerability of processors to soft errors induced by charge carrying particles. Since these factors are only consequences of the inevitable advancement in processor technology, the industry has been forced to improve reliability on general purpose Chip Multiprocessors (CMPs). With the availability of increased hardware resources, redundancy based techniques are the most promising methods to eradicate soft error failures in CMP systems. In this talk, I will discuss a novel redundant CMP architecture (UnSync) that utilizes hardware based detection mechanisms (most of which are readily available in the processor), to reduce overheads during error free executions. In the presence of errors (which are infrequent), the always forward execution enabled recovery mechanism provides for resilience in the system. We design a detailed RTL model of our UnSync architecture and perform hardware synthesis to compare the hardware (power/area) overheads incurred. We compare the same with those of the Reunion technique, a state-of-the-art redundant multi-core architecture. I will also discuss results of cycle-accurate simulations over a wide range of SPEC2000, and MiBench benchmarks to evaluate the performance efficiency achieved over that of the Reunion architecture.
Prof. Aviral Shrivastava is Associate Professor in the School of Computing Informatics and Decision Systems Engineering at the Arizona State University, where he has established and heads the Compiler and Microarchitecture Labs (CML) (http://aviral.lab.asu.edu/). He received his Ph.D. and Masters in Information and Computer Science from University of California, Irvine, and bachelors in Computer Science and Engineering from Indian Institute of Technology, Delhi. He is a 2011 NSF CAREER Award Recipient, and recipient of 2012 Outstanding Junior Researcher in CSE at ASU. His research lies at the intersection of compilers and architectures of embedded and multi-core systems, with the goal of improving power, performance, temperature, energy, reliability and robustness. His research is funded by NSF and several industries including Microsoft, Raytheon Missile Systems, Intel, Nvidia, etc. He serves on organizing and program committees of several premier embedded system conferences, including ISLPED, CODES+ISSS, CASES and LCTES, and regularly serves on NSF and DOE review panels. Right now, he is a visiting faculty in the EECS department at University of California, Berkeley.
As manufacturing processes scale to small feature sizes, devices are more likely to either be defective or experience transient upsets, early performance degradation, and even failure in the field. While redundancy at has long been applied at various levels of design abstraction in order to meet safety goals in critical systems, the above emerging challenges are forcing more and more designers to consider resilience to failure as either an optimization objective or constraint. When cost is also a constraint, as is the case for most embedded, new techniques are needed to effectively and efficiently identify designs that strike the appropriate application-specific trade-offs of resilience and other objectives. In this talk, we will look at the different ways that application, architecture, and failure mechanism interact at the system level to influence the use of redundancy to (a) optimize lifetime and yield in NoC-based MPSoCs, (b) meet safety requirements in mixed-criticality systems, and (c) trade-off performance and yield in multi-core SIMD architectures. In each case, we'll observe that design goals are most effectively met when traditional system-level redundancy strategies are set aside in favor of architectures and automation techniques that leverage insights about the targeted applications.
Prof. Brett H. Meyer is a Chwang-Seto Faculty Scholar and assistant professor in the Department of Electrical and Computer Engineering at McGill University. He received his MS and PhD in Electrical and Computer Engineering from Carnegie Mellon University in 2005 and 2009, respectively. He received his BS in Electrical Engineering, Computer Science and Math from the University of Wisconsin-Madison in 2003. After receiving his PhD, Meyer worked as a post-doctoral research associate in the Computer Science Department at the University of Virginia. He has been on the faculty at McGill since 2011. Meyer’s research interests are focused on the design and architecture of resilient multiprocessor computer systems.
With continuous technology downscaling, the rate of radiation induced soft errors is rapidly increasing. Fast and accurate soft error vulnerability analysis in early design stages plays an important role in cost-effective reliability improvement. However, existing solutions are suitable for either regular (a.k.a address-based such as memory hierarchy) or irregular (random logic such as functional units and control logic) structures, failing to provide an accurate system level analysis. In this talk, a hybrid approach considering both the architecture- and logic-level factors to accurately estimate soft error vulnerability of all regular and irregular structures within a microprocessor is presented. This method carefully handles error propagation and masking scenarios among these structures.
Prof. Mehdi Tahoori is a full professor and the Chair of Dependable Nano-Computing at the Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany. He received his PhD and M.S degrees in Electrical Engineering from Stanford University in 2003 and 2002, respectively, and a B.S. in Computer Engineering from Sharif University of Technology, Iran, in 2000. From 2003 to 2009, he was an assistant/associate professor of Electrical and Computer Engineering at Northeastern University, Boston, MA. In addition to five pending and granted U.S. and international patents for his work, he has over 150 publications in major journals and conference proceedings on various aspects of dependable computing and emerging nanotechnologies. He was a recipient of NSF Early Faculty Development (CAREER) award.
We make the case for developing software that may by design behave non-deterministically but still good enough for a given purpose. The goal is to increase performance and efficiency, potentially by orders of magnitude, but also to increase robustness in the sense that bugs are more likely to be tolerated due to relaxed correctness requirements. As example, we show that concurrent FIFO queues may be implemented on shared memory, large-scale multicore hardware such that queue access throughput scales with the number of cores near-linearly if bounded out-of-FIFO-order queueing is permitted and properly exploited. Moreover, we argue that such increased performance may in fact outweigh the semantical effect of relaxed correctness. In other words, we argue that strict but slow FIFO queues can be seen as behaving more out-of-FIFO order than fast but relaxed FIFO queues.
Prof. Christoph Kirsch is full professor and holds a chair at the Department of Computer Sciences of the University of Salzburg, Austria. Since 2008 he is also a visiting scholar at the Department of Civil and Environmental Engineering of the University of California, Berkeley. He received his Dr.Ing. degree from Saarland University, Saarbruecken, Germany, in 1999 while at the Max Planck Institute for Computer Science. From 1999 to 2004 he worked as Postdoctoral Researcher at the Department of Electrical Engineering and Computer Sciences of the University of California, Berkeley. His research interests are in concurrent programming and systems, virtual execution environments, and embedded software. Dr. Kirsch co-invented the Giotto and HTL languages, and leads the JAviator UAV project for which he received an IBM faculty award in 2007. He co-founded the International Conference on Embedded Software (EMSOFT), has been elected ACM SIGBED chair in 2011, and is currently associate editor of ACM TODAES.
Professor Rakesh Kumar, University of Illinois at Urbana Champaign
Much recent research suggests significant power and energy benefits of relaxing correctness constraints in future processors. Such processors with relaxed constraints have often been referred to as stochastic processors. In this talk, I will discuss three approaches for building applications for such processors. The first approach relies on relaxing the correctness of the application based upon an analysis of application characteristics. The second approach relies upon detecting and then correcting faults within the application as they arise. The third approach transforms applications into more error tolerant forms. In this paper, we show how these techniques that enhance or exploit the error tolerance of applications can yield significant power and energy benefits when computed on stochastic processors.
Prof. Rakesh Kumar is an Assistant Professor in the Electrical and Computer Engineering Department at the University of Illinois at Urbana Champaign. He received a B.Tech. degree in Computer Science and Engineering from the Indian Institute of Technology (IIT), Kharagpur in 2001 and a Ph.D. degree in Computer Engineering from the University of California, San Diego in September 2006. Prior to moving to Champaign in 2007, he was a visiting researcher with Microsoft Research at Redmond. His research interests include reliable and low power computing. His past research on heterogeneous multi-core architecture and conjoined-core architectures has directly influenced processor products and roadmaps from several companies. His current research interests are in error resilient computer systems and low power computer architectures for emerging workloads. His research has been recognized by several awards, including Best Paper Awards (CASES 2011, SRC TECHCON 2011), Best Paper Award Nominations (HPCA 2012), ARO Young Investigator Award, Arnold O Beckman Research Award, FAA Creative Research Award, UCSD CSE Best Dissertation Award, and an IBM PhD Fellowship. Other recognitions include Keynote Invitations (CASA 2012, WRA 2011, WDSN 2011, LPonTR 2011), Invited/Plenary lectures at over twenty conferences and workshops (DAC, CASES, ISLPED, IOLTS, etc.), and Invited Guest Editorships (IEEE Transactions on Multimedia, IEEE Embedded Systems Letters). He has served as a Chair of two Workshops in the area of robust computing and multi-core computing (SELSE 2011 and dasCMP 2005-2008). When not doing computing research, he enjoys studying interactions between technology, policy, and society.