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Multi-core Computing Challenge: Missing Memory Virtualization Purdue University, West Lafayette, IN, April 2011. |
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Multi-core Computing Challenge: Missing Memory Virtualization University of Pennsylvania, Philiadelphia, PA, April 2011. |
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Multi-core Computing Challenge: Missing Memory Virtualization University of California, San Diego, San Diego, CA, April 2011. |
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Multi-core Computing Challenge: Missing Memory Virtualization Georgia Institute of Technology, Atlanta, GA, March 2011. |
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Multi-core Computing Challenge: Missing Memory Virtualization UT Austin, Austin, TX, March 2011. |
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Multi-core Computing Challenge: Missing Memory Virtualization Columbia University, New York, NY, March 2011. |
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Multi-core Computing Challenge: Missing Memory Virtualization IIT Delhi, Delhi, India, Jan 2011. |
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Multi-core Computing Challenge: Missing Memory Virtualization IIT Ropar Ropar, India, Jan 2011. |
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Compilation for Hybrid Cache and SPM Memory Hierarchy Texas Instruments Houston, TX, August 2010. |
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Research on Low-Power Compilation Marvell Semiconductors Chandler, AZ, July 2010. |
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Compilation for IBM Cell Rainbow Studios, Phoenix, AZ, June 2010. |
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Multi-core Programming - A 2-day Professional Course Arizona State University, Tempe, AZ, Aug 2009. |
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Compiler-Aided Soft Error Protection of Register File Caltech Center for Advanced Computing Research, Pasadena, California, July 2009. |
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Compiler-enabled Power-Efficient Register File Protection Space Mission Challenges - Information Technology (SMC-IT 2009), Pasadena, California, July 2009. |
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Multi-core Computing Challenge: Missing Memory Virtualization Texas Instruments, Houston, Texas, Jan 2009. |
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Multi-core Computing Challenge: Missing Memory Virtualization IBM India Research Laboratories, New Delhi, India, Jan 2009. |
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The Growth of Computing and Multi-core Challenges SISTEC, Bhopal, India, Dec 2008. |
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Scratch Pad Memories: Life Beyond Embedded Systems Compiler Assisted SoC Assembly Workshop, Atlanta, Oct 2008. |
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Compiler and Microarchitectural Techniques for Leakage Reduction BK21 Workshop Seoul National University>, Seoul, South Korea, 2008 |
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Application Mapping onto Coarse-Grain Reconfigurable Architectures ETRI, Seoul, South Korea, 2008 |
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Compiler and Microarchitectural Techniques for Low Power Microsoft Research, Redmond, WA, 2007. |
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Compiler and Microarchitectural Techniques for Low Power LSI Systems, San Jose, 2007 |
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Compiler Techniques for Power Reduction in Embedded Processors NSF IUCRC Workshop at ASU, Tempe, AZ, 2007 |
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Architecture-Sensitive Compiler Techniques for Energy Reduction Coware Inc., Noida, India, 2007 |
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Compiler-in-the-Loop Exploration of Embedded Systems Indian Institute of Technology, Delhi, India, 2007 |
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Compiler-in-the-Loop Exploration of Embedded Systems Indian Institute of Sciences, Bangalore, 2007 |
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Compiler-assisted Processor Exploration and Design Workshop on Compiler Assisted SoC Assembly 2006 |
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Architecture Sensitive Compilation Techniques for Energy Reduction Apple Inc. Cupertino, CA, 2006 |
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Architecture Sensitive Compilation Techniques for Energy Reduction SO&R Labs, Seoul National University, South Korea, 2006 |
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Compiler-in-the-Loop Exploration of Programmable SoCs Optimizing Compiler Assisted SoC Assembly Workshop 2005 |
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Compiler-in-the-loop Design Space Exploration of XScale
Microarchitectures using EXPRESSION ADL VSSAD, Intel, Hudson, 2005 |
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Compiler Optimizations for Performance and Energy Improvements in
Simple In-order Processors Strategic CAD Labs, Intel, 2003 |