Compiler-Microarchitecture Lab: Research

Department of Computer Science
School of Computing, Informatics and Decision Systems Engineering
Arizona State University

Research Themes

[LLM]

Multi-cores provide a way to continue increasing performance, without much increase in the power consumption of the processor. One major challenge in developing multi-core architectures is scaling of memory hierarchy. Limited Local Memory, or LLM architectures are scalable multi-core designs that have a small local memory in each core, e.g., the IBM Cell. Our research objective is to automatically compile for these architectures and make them usable.

[CGRA]

Developing computer systems that achieve high performance at high power efficiency is the holy grail of computer architecture. Coarse Grain Reconfigurable Architectures or CGRAs are just a 2 dimensional mesh of processing elements or PEs (an ALU + a few registers). CGRAs can achieve very high power-efficiency, 10-100X that of current cores. However, challenges remain in compilation for them.

[SER]

As technology continues to scale, and feature size become every so smaller, transistors become increasingly vulnerable to soft errors. Soft errors -- typically caused by cosmic particle strike on transistors -- can change the logic value of the transistor. Our research seeks to develop architectures and compiler techniques to mitigate the impact of soft errors. Compiler techniques can reduce the impact of soft errors by changing the computation to use processor resources that are protected, and perform computation in a redundant fashion.

[rISA]

Code size is an important constraint for many embedded systems, especially the ones in which the code is burnt on ROMs, which can be the major component on the chip. Dual instruction set, one composed of full width instructions, and another composed of narrow instructions is a promising approach to reduce code size. Our research efforts are towards developing tools and techniques to compile for such reduced bit-width Instruction Set Architectures.

[BAC]

Bypasses are important in pipelined processors to eliminate some of the data dependencies. However, the hardware overhead of adding bypasses is very significant. Because of increased wiring costs, they may result in an increase in cycle time and overall area. Therefore the question in embedded systems is, which bypasses to have, so that minimal performance is sacrificed, at minimal hardware overhead. Our research on developing bypass sensitive compiler can help designers explore which bypasses to have.

[PICA]

During execution, a processor is typically stalled for a significant amount of time doing nothing, but waiting for data from memory. However, these stall durations are typically small. Our research in this area is to aggregate these small but several stall cycles to create a larger stall, during which the processor can be switched to a lower-power mode.

[PVT]

Power consumption, process variations, and temperature are all problems due to techology scaling to incredible levels. Our approach to deal with power, temperature and process variations is to expose them to microarchitecture and software levels, where instruction scheduling and component sleep solutions can be developed to handle these issues.