Adaptive Recuced Bit-width Instruction Set Architecture (adapt-RISA)

Sandro Neves Soares Ashok Halambi, Aviral Shrivastava, Nikil Dutt, Flavio Rech Wagner

VLSI-SOC 2009: Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integreation

Abstract: rISA (reduced bit-width Instruction Set Architecture) is an important architectural feature to reduce code size, which continues to be an extremely important concern for low-end embedded systems. rISA reduces code size by expressing parts of the application in terms of low bit-width instructions. ARM-Thumb, ARCcompact and MIPS16/32 are popular examples. With the intent to exploit the dynamically changing "working instruction set" of today's complex software, ARM 11 now comes with two rISAs, which can be interleaved in the application binary. However, it was demonstrated that the code compression achieved by rISA is extremely sensitive on the selected rISA design. Therefore, it is important to design the optimal rISA for a given embedded application. The one optimal rISA per application approach has already been explored by previous works. In this paper, we present a scheme to design a multiple rISA architecture for embedded systems. Our experiments on MiBench report an average of 19% code compression and up to 7% power reduction of instruction memory when compared to previous approaches using only one optimal rISA.