Compiler-Microarchitecture Lab: Publications

Compiler-Microarchitecture Lab: Publications

Department of Computer Science
School of Computing and Informatics
Arizona State University


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Software Conference Papers Journal Articles Invited Talks Thesis

Software

PTSMT NEW
A Tool for Cross-Level Power, Performance and Thermal Exploration

PBExplore
A Compiler-in-the-Loop Framework to explore Register Bypasses in Pipelined Embedded Processors.

EXPRESSION
An Architecture Description Language (ADL) based Retargetable Compiler-Simulator toolchain.

Book Chapters

ADLBook
ADL-Driven Methodologies for Design Automation of Programmable Architectures NEW
Prabhat Mishra and Aviral Shrivastava
Elsevier 2008, Processor Description Languages: Applications and Methodologies,
ISBN: 978-0-12-374287-2
CDHBook
Compiler Aided Design of Embedded Computers Aviral Shrivastava and Nikil Dutt
CRC Press 2007, The Compiler Design Handbook: Optimizations and Machine Code Generation, Second Edition,
ISBN: 978-1-4200-4382-2

Conference Papers

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bibtex Memory-Aware Application Mapping on Coarse Grain Reconfigurable Arrays NEW
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee Yoon, and Yunheung Paek
HIPEAC 2010 :Proceedings of the 2010 International Conference on High-Performance Embedded Architectures and Compilers
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bibtex Exploiting Residue Number System for Power-Efficient Digital Signal Processing in Embedded Processors NEW
Rooju Chokshi, Krzysztof Berezowski, and Aviral Shrivastava
CASES 2009 :Proceedings of the 2009 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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bibtex A Compiler Optimization to Reduce Soft Errors in Register Files NEW
Jongeun Lee and Aviral Shrivastava
LCTES 2009 :Proceedings of the 2009 ACM SIGPLAN/SIGBED Conference on Language, Compilers and Tool support for Embedded Systems
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bibtex Adaptive Recuced Bit-width Instruction Set Architecture (adapt-RISA) NEW
Sandro Neves Soares, Ashok Halambi, Aviral Shrivastava, Flavio Rech Wagner, and Nikil Dutt
VLSI-SOC 2009 :Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integreation
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bibtex FSAF: File System Aware Flash Translation Layer for NAND Flash Memories NEW
Sai Mylavarapu, Siddharth Chaudhuri, Aviral Shrivastava, Jongeun Lee, and Tony Givargis
DATE 2009 :Proceedings of the International Conference on Design Automation and Test in Europe
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bibtex Static Analysis to Mitigate Soft Errors in Register Files NEW
Jongeun Lee and Aviral Shrivastava
DATE 2009 :Proceedings of the International Conference on Design Automation and Test in Europe
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bibtex A Software Solution for Dynamic Stack Management on Scratch Pad Memory NEW
Arun Kannan, Aviral Shrivastava, Amit Pabalkar and Jongeun Lee
ASPDAC 2009 :Proceedings of the Asia and South Pacific Design Automation Conference
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bibtex Compiler-Managed Register File Protection for Energy-Efficient Soft Error Reduction NEW
Jongeun Lee and Aviral Shrivastava
ASPDAC 2009 :Proceedings of the Asia and South Pacific Design Automation Conference
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bibtex Code Transformations for TLB Power Reduction NEW
Reiley Jeyapaul, Sandeep Marathe, and Aviral Shrivastava
VLSI 2009 :Proceedings of the 22nd International Conference on VLSI Design
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bibtex Static Analysis of Processor Stall Cycle Aggregation
Jongeun Lee and Aviral Shrivastava
CODES+ISSS 2008 :Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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bibtex SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories
Amit Pabalkar, Aviral Shrivastava, Arun Kannan, and Jongeun Lee
HIPC 2008 :International Conference on High Performance Computing
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bibtex Mitigating the Impact of Hardware Failures on Multimedia Applications - A Cross-Layer Approach
Kyoungwoo Lee, Aviral Shrivastava, Minyoung Kim, Nikil Dutt and Nalini Venkatasubramanian
ACM MM 2008 :ACM International Conference on Multimedia
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bibtex Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures
Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt and Nalini Venkatasubramanian
DIPES 2008 :IFIP Conference on Distributed and Parallel Embedded Systems
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bibtex Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
Sanghyun Park, Aviral Shrivastava, and Yunheung Paek
DATE 2008 :Proceedings of the International Conference on Design Automation and Test in Europe
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bibtex SPKM : A Novel Graph Drawing based Algorithm for Application Mapping onto Coarse-Grained Reconfigurable Architecture
Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn and Yunheung Paek
ASPDAC 2008 :Proceedings of the Asia and South Pacific Design Automation Conference
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bibtex A Compiler-in-the-Loop Framework for Exploration of Horizontally Partitioned Caches
Aviral Shrivastava, Ilya Issenin, and Nikil Dutt
ASPDAC 2008 :Proceedings of the Asia and South Pacific Design Automation Conference
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bibtex PTSMT: A Tool for Cross-Level Power, Performance and Thermal Exploration
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Fadi Kurdahi, and Nikil Dutt
VLSI 2008 :Proceedings of the 21st International Conference on VLSI Design
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bibtex Temperature and Process Variations aware Power Gating of Functional Units
Deepa Kannan, Vipin Mohan, Sarvesh Bharadwaj, Aviral Shrivastava and Sarma Vrudhula
VLSI 2008 :Proceedings of the 21st International Conference on VLSI Design
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bibtex Power Reduction of Functional Units considering Temperature and Process Variations
Deepa Kannan, Sarvesh Bharadwaj, Aviral Shrivastava and Sarma Vrudhula
VLSI 2008 :Proceedings of the 21st International Conference on VLSI Design
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bibtex Smart Driver for Power Reduction in Next Generation Bi-Stable Electrophoretic Display Technology
Michael Baker, Aviral Shrivastava and Karam Chatha
CODES+ISSS 2007 :Proceedings of the 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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bibtex Power Conscious Mapping onto Coarse-Grained Reconfigurable Architectures using Graph Drawing based Algorithm
Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, and Yunheung Paek
WASP 2007 :Workshop on Application Specific Processors
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bibtex Functional and Timing Validation of Partially Bypassed Processors
Qiang Zhu, Aviral Shrivastava, and Nikil Dutt
DATE 2007 :Proceedings of the International Conference on Design Automation and Test in Europe
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bibtex Robust Localization in Wireless Sensor Networks through the Revocation of Malicious Anchors
Satyajayant Mishra, Guoliang Xue, and Aviral Shrivastava
ICC 2007 :Proceedings of the International Conference on Communications
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bibtex Mitigating Soft Error Failures for Multimedia Applications by Selective Data Protection
Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt and Nalini Venkatasubramanian
CASES 2006 :Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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bibtex Bypass Aware Instruction Scheduling for Register File Power Reduction
Sanghyun Park, Aviral Shrivastava, Nikil Dutt, Alex Nicolau, Eugene Earlie, and Yunheung Paek
LCTES 2006 :Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers and tool support for embedded systems
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bibtex Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors
Sanghyun Park, Aviral Shrivastava, Nikil Dutt, Alex Nicolau, Eugene Earlie, and Yunheung Paek
DATE 2006 :Proceedings of the International Conference on Design Automation and Test in Europe
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bibtex Compilation Techniques for Energy Reduction in Horizontally Partitioned Cache Architectures
Aviral Shrivastava, Ilya Issenin and Nikil Dutt
CASES 2005 :Proceedings of the 2005 International Conference on Compilers, Architectures and Synthesis for Embedded Systems on Hardware/Software Codesign and System Synthesis
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bibtex Aggregating Processor Free Time for Energy Reduction
Aviral Shrivastava, Eugene Earlie, Nikil Dutt, and Alex Nicolau
CODES+ISSS 2005 :Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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bibtex PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors
Aviral Shrivastava, Eugene Earlie, Nikil Dutt, and Alex Nicolau
DATE 2005 :Proceedings of the International Conference on Design Automation and Test in Europe
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Compiler-in-the-Loop, ADL-driven Early Architectural Exploration
Aviral Shrivastava, Nikil Dutt, Alex Nicolau, and Eugene Earlie
TECHCON 2005 :Semiconductor Research Corporation
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bibtex Operation Tables for Scheduling in the Presence of Partial Bypassing
Aviral Shrivastava, Eugene Earlie, Nikil Dutt, and Alex Nicolau
CODES+ISSS 2004 :Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis
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bibtex Energy Efficient Code Generation using rISA
Aviral Shrivastava and Nikil Dutt
ASPDAC 2004 :Proceedings of the Asia and South Pacific Design Automation Conference
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bibtex A Design Space Exploration Framework for Reduced Bit-width Instruction Set Architecture (rISA) Design
Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil Dutt, and Alex Nicolau
ISSS 2002 :Proceedings of the International Symposium on System Synthesis
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bibtex An Efficient Compiler Technique for Code Size Reduction using Reduced Bit-width ISAs
Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil Dutt, and Alex Nicolau
DATE 2002 :Proceedings of the International Conference on Design Automation and Test in Europe
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A Customizable Compiler Framework for Embedded Systems
Ashok Halambi, Aviral Shrivastava, Nikil Dutt, and Alex Nicolau
SCOPES 2001 :International Workshop on Software and Compilers for Embedded Systems
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bibtex Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming
Aviral Shrivastava, Mohit Kumar, Sanjeev Kapoor, Shashi Kumar, and M. Balakrishnan
VLSI 2000 :Proceedings of the 13th International Conference on VLSI Design


Journal Articles

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bibtex A Software-only solution to use Scratch Pads for Stack Data NEW
Aviral Shrivastava, Arun Kannan, and Jongeun Lee
TCAD :IEEE Transactions on Computer Aided Design (Accepted)
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bibtex Reducing Functional Unit Power Consumption and its Variation using Leakage Sensors NEW
Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj, and Sarma Vrudhula
TVLSI :IEEE Transactions on Very Large Scale Integration Systems (Accepted)
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bibtex Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures NEW
Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Sanghyun Park, and Yunheung Paek
TCAD :IEEE Transactions on Computer Aided Design (Accepted)
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bibtex A Graph Drawing Based Spatial Mapping Algorithm for Coarse- Grained Reconfigurable Architectures NEW
Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, and Yunheung Paek
TVLSI :IEEE Transactions on VLSI (Accepted)
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bibtex Partially Protected Caches to Reduce Failures due to Soft Errors in Multimedia Applications NEW
Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Nalini Venkatasubramanian
TVLSI :IEEE Transactions on VLSI (Accepted)
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bibtex Register File Power Reduction Using Bypass Sensitive Compiler
Sanghyun Park, Aviral Shrivastava, Nikil Dutt, Alex Nicolau, Yunheung Paek, Eugene Earlie
TCAD :IEEE Transactions on Computer Aided Design, June 2008
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bibtex Automatic Design Space Exploration of Register Bypasses in Embedded Processors
Sanghyun Park, Aviral Shrivastava, Eugene Earlie, Nikil Dutt, Alex Nicolau, and Yunheung Paek
TCAD :IEEE Transactions on Computer Aided Design, December 2007
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bibtex ADL-driven Software Toolkit Generation for Architectural Exploration of Programmable SOCs
Prabhat Mishra, Aviral Shrivastava and Nikil Dutt
TODAES :ACM Transactions on Design Automation of Electronic Systems, July 2006.
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bibtex Retargetable Pipeline Hazard Detection for Partially Bypassed Processors
Aviral Shrivastava, Nikil Dutt, Alex Nicolau, and Eugene Earlie
TVLSI :IEEE Transactions on VLSI, August 2006
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bibtex Compilation Framework for Code Size Reduction using Reduced Bit-width ISAs
Aviral Shrivastava, Ashok Halambi, Partha Biswas, Nikil Dutt, and Alex Nicolau
TODAES :ACM Transactions on Design Automation of Electronic Systems, January 2006.

Selected Talks

Multi-core Programming - A 2-day Professional Course
Arizona State University, Tempe, AZ, Aug 2009.
Compiler-Aided Soft Error Protection of Register File
Caltech Center for Advanced Computing Research, Pasadena, California, July 2009.
Compiler-enabled Power-Efficient Register File Protection
Space Mission Challenges - Information Technology (SMC-IT 2009), Pasadena, California, July 2009.
Multi-core Computing Challenge: Missing Memory Virtualization
Texas Instruments, Houston, Texas, Jan 2009.
Multi-core Computing Challenge: Missing Memory Virtualization
IBM India Research Laboratories, New Delhi, India, Jan 2009.
The Growth of Computing and Multi-core Challenges
SISTEC, Bhopal, India, Dec 2008.
Scratch Pad Memories: Life Beyond Embedded Systems
Compiler Assisted SoC Assembly Workshop, Atlanta, Oct 2008.
Compiler and Microarchitectural Techniques for Leakage Reduction
BK21 Workshop Seoul National University>, Seoul, South Korea, 2008
Application Mapping onto Coarse-Grain Reconfigurable Architectures
ETRI, Seoul, South Korea, 2008
Compiler and Microarchitectural Techniques for Low Power
Microsoft Research, Redmond, WA, 2007.
Compiler and Microarchitectural Techniques for Low Power
LSI Systems, San Jose, 2007
Compiler Techniques for Power Reduction in Embedded Processors
NSF IUCRC Workshop at ASU, Tempe, AZ, 2007
Architecture-Sensitive Compiler Techniques for Energy Reduction
Coware Inc., Noida, India, 2007
Compiler-in-the-Loop Exploration of Embedded Systems
Indian Institute of Technology, Delhi, India, 2007
Compiler-in-the-Loop Exploration of Embedded Systems
Indian Institute of Sciences, Bangalore, 2007
Compiler-assisted Processor Exploration and Design
Workshop on Compiler Assisted SoC Assembly 2006
Architecture Sensitive Compilation Techniques for Energy Reduction
Apple Inc. Cupertino, CA, 2006
Architecture Sensitive Compilation Techniques for Energy Reduction
SO&R Labs, Seoul National University, South Korea, 2006
Compiler-in-the-Loop Exploration of Programmable SoCs
Optimizing Compiler Assisted SoC Assembly Workshop 2005
Compiler-in-the-loop Design Space Exploration of XScale Microarchitectures using EXPRESSION ADL
VSSAD, Intel, Hudson, 2005
Compiler Optimizations for Performance and Energy Improvements in Simple In-order Processors
Strategic CAD Labs, Intel, 2003

Ph.D. Thesis

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Aviral Shrivastava
Compiler-in-Loop Exploration of Programmable Embedded Systems
Advisors: Nikil Dutt (Chair), Alex Nicolau, Alex Veidenbaum.


Masters Thesis

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Arun Kannan
A Software-Only Solution for Stack Management on Systems with Scratch Pad Memory
Advisors: Aviral Shrivastava (Chair), Charles Colburn, Rida Bazzi
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Amit Pabalkar
A Dynamic Code Mapping Technique for Scratch Pad Memories in Embedded Systems
Advisors: Aviral Shrivastava (Chair), Karama Chatha, Partha Dasgupta
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Rooju Chokshi
Residue number system enhancements for programmable processors
Advisors: Aviral Shrivastava (Chair), Sarma Vrudhula, Rida Bazzi
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Sai Mylavarapu
Improving Application Response Times of Nand Flash based Systems
Advisors: Aviral Shrivastava (Chair), Karam Chatha, Rida Bazzi