Spring 2009: CSE 591
Low Power Computer Architecture
Course Outcome: 2 papers submitted in international conferences
- LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant
Caches, submitted to DATE 2010
- Exploring Power-Accuracy Trade-offs for Supporting Human Activity
Transition Detection, submitted to DATE 2010
Course Information
- Instructor: Aviral Shrivastava
- Lecture Location: TBD
- Lecture Time: TBD
- Office Hours: TBD
Course Abstract
For the past 4 decades performance has been the main driver behind the
evolution of processor architectures.
However, relentless technology scaling has brought us to a point,
where the power consumption has become the main design concern of
system designers.
The processor market is now increasingly being classified in terms of
power consumption rather than performance.
For example, you can hear processor companies talk about their desire
to have a processor in the sub-watt range.
This course will quickly gloss over the basic process-level,
transistor-level, and circuit level techniques for power redcution.
We will spend some time on methods of power characterization and
estimation at the microarchitecture level.
Our concentration will be on solutions to the power problem at the
microarchitecture, compiler and system level.
The projects will involve proposing and implementing novel power
optimization technique.
The ultimate metric of success in this class will be publishable
quality work.
Course Contents
- Motivation for Low Power Computer Design
- Short Tutorial on Computer Architecture
- Instruction Level Power Estimation
- Microarchitecture Level Power Estimation
- Battery Modeling
- Throttling
- Processor Pipeline
- Power Gating
- Register File Power Reduction
- Chip MultiProcessors
- Feul and Solar Cells
- Flash Memory
Course Structure
- Classroom: This course is organized as a discussion course with
each class meeting allocated to the discussion of a particular topic.
Before each meeting, all students are expected to read three or four
papers describing recent research on that topic.
Two student will be responsible for leading each discussion and one
student will be a scribe for each meeting, responsible for recording
and writing up the discussion.
- There will be two programming assignments, the first one simple,
just to get started, and the second one will be the main.
The focus will be on novel and useful microarchitectural,compiler, or
system level idea for power reduction.
- There will be no homework assignments and no exams.
Grading
- Paper presentation: 20%
- Class participation: 10%
- Project 1 - Report (1-2 page): 10%
- Project 1 - Software Demo: 10%
- Project 2 - Proposal (1-2 page): 10%
- Project 2 - Paper (6-10 page): 20%
- Project 2 - Software Demo: 20%