Chaitali Chakrabarti received her B. Tech. in Electronics and Electrical
Communication Engineering from the Indian Institute of Technology,
Kharagpur, India in 1984. She received her M.S. and Ph.D. in
Electrical Engineering Dept
from
U. of Maryland, College Park in 1986 and 1990 respectively.
She has been at ASU since fall 1990.
Chaitali's research interests are in the areas
of VLSI architectures for
signal processing and communications, algorithm-architecture
co-design of signal processing systems,
and all aspects of low power embedded system design
including those that operate at near-threshold voltages.
She received Best Paper Awards at SAMOS'07 for "The Next Generation Challenge for
Software Defined Radio," at MICRO'08 for "From SODA to Scotch: The Evolution of
a Wireless Baseband Processor," and at SiPS'10 for "A New Parallel Implementation
for Particle Filters and its Application to Adaptive Waveform Design".
Chaitali is a member of the
SenSIP .
She is an Associate Editor of the
Journal of VLSI Signal Processing Systems (1999-present) and
the IEEE Transactions on VLSI Systems (2007-present). She also
served as the Associate Editor of IEEE Trans on Signal Processing
(1999-2005) and as
the Chair of the Technical Committee on
Design and Implementation
of Signal Processing Systems , IEEE Signal Processing Society,
(2006-2007). She is a Fellow of the IEEE.
Chaitali teaches undergraduate courses on Digital Design Fundamentals,
Signals and Systems, Basic Circuits,
Digital Systems and Circuits as well as the
graduate courses on VLSI Design, and VLSI
architectures. She is the recepient of the
1994 CEAS Young Faculty Teaching
Excellence award, the 2001 IEEE
Phoenix Chapter's Outstanding
Educator award and the 2012 Top Five Percent Faculty
at the Ira A. Fulton Schools of Engineering Award.
Bio
Research Interests:
Low Power System Design
VLSI Implementations of Signal Processing and Communication Systems
Publications:
Here are online versions of
publications (93- ).
Courses: