Chaitali Chakrabarti
Professor

School of Electrial, Computer and Energy Engg.,
Ira A. Fulton Schools of Engineering
Arizona State University, Tempe Arizona 85287-5706
Phone: (480) 965-9516, Fax: (480) 965-8325, Email: chaitali@asu.edu


Papers from Chaitali Chakrabarti's group

Papers from Chaitali Chakrabarti's group

Contact Chaitali Chakrabarti email if you have questions or need further information.

2023

  1. Cyclebite: Extracting Task Graphs from Unstructured Compute Programs
    B. Willis, A. Shrivastava, J. Mack, S. Dave. C. Chakrabarti and J. Brunhaver
    IEEE Transactions on Computers, pp. 221-234, Oct 2023.

  2. PED: Probabilistic Energy-Efficient Deadline-Aware Scheduler for Heterogeneous Socs
    X. Chen, A. Krishnakumar, U.Y. Ogras and C. Chakrabarti
    Journal of Systems Architectures, vol. 147, pp 103051.

  3. FALCON: An FPGA Emulation Platform for Domain-Specific Systems-on-Chip (DSSoCs)
    A. Krishnakumar, H. Yu, T. Ajayi, A. Alper Goksoy, V. Pandey, J. Mack, S. Hassan, K.-Y. Chen, C. Chakrabarti, D. W. Bliss, A. Akoglu, H.-S. Kim, R. G. Dreslinski, D. Blaauw and U. Y. Ogras
    IEEE Design and Test, pp. 70-80, March 2023.

  4. Proactively Predicting Dynamic 6G Link Blockages using LiDAR and In-band Signatures
    S. Wu, C. Chakrabarti and A. Alkhateeb
    IEEE Open Journal of the Communications Society, pp. 392-412, Jan 2023.

  5. Communications and High-precision Positioning (CHP2): Hardware Architecture, Implementation and Validation
    H. Yu, A. Hertschfelt, S. Wu, S. Srinivas, Y. Li, N. Sciammetta, L. Smith, K. Reuger, H. Lee, C. Chakrabarti and D.W. Bliss
    Sensors, article 1343, 2023.

  6. Aligning Speech Enhancement for Improving Downstream Classification Performance
    Y, Xiong, V. Berisha and C. Chakrabarti
    Proc. of INTERSPEECH, 2023.

  7. MocoSFL: Enabling Cross-client Collaborative Self-supervised Learning
    J. Li, L. Lyu, D. Iso, C. Chakrabarti and M. Spranger
    Proc. of International Conference on Learning Representations (ICLR), 2023. Top 5% paper.

2022

  1. Energy and Loss-Aware Selective Updating for SplitFed Learning with Energy Harvesting-Powered Devices
    X. Chen, J. Li and C. Chakrabarti
    Journal of Signal Processing Systems, 94(10, pp. 961-975, 2022.

  2. Versa: A 36 core Systolic Multiprocessor with Dynamically Reconfigurable Interconnect and Memory
    S. Kim, M. Fayazi, A. Daftardar, K.-Y. Chen, J. Tan, S. Pal, Y. Xiong, T. Mudge, C. Chakrabarti, D. Blaauw, R. Dreslinski and H.-S. Kim
    IEEE Journal of Solid State Circuits, 75(4), pp. 986-998, April 2022.

  3. Blockage Prediction using Wireless Signatures: Deep Learning Enables Real-World Demonstrations
    S. Wu, M. Alrabeiah, C. Chakrabarti and A. Alkhateeb
    IEEE Open Journal of the Communications Society, 3, pp. 776-796, 2022.

  4. Probabilistic Risk-Aware Scheduling with Deadline Constraints for Heterogeneous SoCs
    X. Chen, U. Ogras and C. Chakrabarti
    ACM Transactions on Embedded Computing Systems, 21(2), 15;1-15:27, 2022.

  5. Impact of On-chip Interconnect in In-memory Acceleration of Deep Neural Networks
    G. Krishnan, S. K. Mandal, C. Chakrabarti, J. Seo, U. Ogras and Y. Cao
    ACM Journal on Emerging Technologies in Computing Systems, 18(2), 34:1-34:22, 2022.

  6. T-BFA: Targeted Bit-Flip Adversarial Weight Attack
    A. Rakin, Z. He, J. Li, F. Yao, C. Chakrabarti and D. Fan
    IEEE Transactions on Pattern Analysis and Machine Intelligence, 44(11), pp. 7928-7939, 2022.

  7. Profile-Guided Parallel Task Extraction and Execution for Domain-Specific Heterogeneous SoC
    L. Chang, J. Mack. B. Willis, X. Chen, J. Brunhaver, A. Akoglu and C. Chakrabarti
    Proc. of International Symposium on Parallel and Distributed Processing (ISPA), Dec 2022.

  8. AI Computing in Light of 2.5D Interconnect Roadmap: Big-Little Chiplets for In-Memory Acceleration
    Z. Wang, G. R. Nair, G. Krishnan, S. Mandal, N. Cherian, J. Seo, C. Chakrabarti, U. Ogras and Y. Cao
    Proc. of International Electronic Devices Meeting (IEDM), Dec 2022.

  9. Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architectuire
    G. Krishnan, A. Goksoy, S. Mandal, Z. Wang, C. Chakrabarti, J. Seo, U. Ogras and Y. Cao
    Proc. of IEEE International Conference on Computer Aided Design (ICCAD), Nov 2022.

  10. An Adjustable Farthest Point Sampling Method for Approximately Sorted Point Cloud Data
    J. Li, J. Zhou, Y. Xiong, X. Chen and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems (SiPS), Oct 2022.

  11. ResSFL: A Resistance Transfer Framework for Defending Model Inversion Attack in Split Federated Learning
    J. Li, A. S. Rakin, X. Chen, Z. He, D. Fan and. C. Chakrabarti
    proc. of IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), June 2022.

  12. Deep Learning for Blockage Prediction using Real Millimeter Wave Measurements
    S. Wu, M. Alrabeiah, A. Hredzak, C. Chakrabarti and A. Alkhateeb
    Proc. of IEEE International Conference on Communications (ICC), May 2022.

  13. Improving Energy Efficiency of Convolutional Neural Networks on Multi-core Architectures through Run-time Reconfiguration
    Y. Xiong, J. Li, D. Blaauw, H.-S. Kim, T. Mudge, R. Dreslinski and C. Chakrabarti
    Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), May 2022.

  14. Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor
    D. W. Bliss and et. al
    Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), May 2022.

2021

  1. SIAM: Chiplet-based Scalable In-memory Acceleration with Mesh for Deep Neural Networks.
    G. Krishnan, S. Mandal, M. Pannala, C. Chakrabarti, J. Seo, Y. Cao and U. Ogras
    ACM Transactions on Embedded Computing Systems, 2021.

  2. Front-end Architecture Design for Low Complexity 3D Ultrasound Imaging based on Synthetic Aperture Sequential Beamforming
    J. Zhou, S. Mandal, B. West, S. Wei, U. Ogras, O.Kripfgans, J.B.Fowles, T.F. Wenisch and C. Chakrabarti
    IEEE Transactions on VLSI Systems, 29(2), pp. 336-346, 2021.

  3. CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics
    S. Feng, J. Sun, S. Pal, K. Kaszyk, X. he, D.-H. Park, M. Morton, D. Blaauw, H.-S. Kim, T. Mudhe, M. Cole, M. O'Boyle, C. Chakrabarti amd R. Dreslinski
    Proc. of Design Automation Conference (DAC), Dec 2021.

  4. NeurObfuscator: A Full-stack Obfuscation Tool to Mitigate Neural Architecture Stealing
    J. Li, A. Rakin, Z. He, D. Fan and C. Chakrabarti
    International Symposium on Hardware Oriented Security and Trust (HOST), Dec 2021.

  5. System-level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration
    G. Krishnan, S. Mandal, C. Chakrabarti, J. Seo, U. Ogras and Y. Cao
    IEEE 14th International Conference on ASIC, China, Oct 2021.

  6. Communication and Computation Reduction in Split Learning using Asynchronous Training
    X. Chen, J. Li and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems (SiPS), Oct 2021.

  7. Computationally-efficient Voice Activity Detection based on Deep Neural Networks
    Y. Xiong, V. Berisha and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems (SiPS), Oct 2021.

  8. Versa: A Dataflow-centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28 nm
    S. Kim, M. Fayazi, A. Daftardar, K.-Y. Chen, J. Tan, S. Pal, T. Ajayi, Y. Xiong, T. Mudge, C. Chakrabarti, D. Blaauw, R. Dreslinski and H.-S. Kim
    Proc. of VLSI Symposium, May 2021.

  9. RADAR: Run-time Adversarial Weight Attack Detection and Accuracy Recovery
    J. Li, A. Rakin, Z. He. D. Fan and C. Chakrabarti Proc. of Design and Test in Europe (DATE), Feb 2021.

2020

  1. TETRIS: Using Software/Hardware Co-Design to Enable Handheld physice-Limited 2D Plane-Wave Ultrasound Imaging
    B. West, J. Zhou, R. Dreslinski, O. Kripfgans, J.B.Fowles, C. Chakrabarti and T.F. Wenisch
    Special Issue on Dpomain-Specific Architectures for Emerging Applications, IEEE Transactions on Computers, 69(8), pp. 1209-1220, 2020.

  2. Parallel Gibbs Sampler for Wavelet-based Bayesian Compressive Sensing
    J. Zhou, A. Papamdreou-Suppappola and C. Chakrabarti
    Journal of Signal Processing Systems, 92(10), pp.1101-1114, 2020.

  3. Interconnect-aware Area and Energy Optimization for In-memory Acceleration of DNN
    S. Mandal, G. Krishnan, C. Chakrabarti, J.-S. Seo, U. Ogras and Y. Cao
    IEEE Design and Test, 2020.

  4. A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNN
    S. Mandal, G. Krishnan, C. Chakrabarti, J.-S. Seo, Y. Cao and U. Ogras
    IEEE Journal of Emerging Selected Topics in Circuits and Systems, 10(3), pp. 362-375, 2020.

  5. A 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-grain Sparsity with All Parameters Stored on-Chip
    D. Kadetotad, S. Yin, V. Berisha, C. Chakrabarti and J.-S. Seo
    IEEE Journal of Solid State Circuits, 55(7), pp. 1877-1887, 2020.

  6. A 7.3M Output Non-zeros/J, 11.7M Output Non-zeros/GB Reconfigurable Sparse Matrix-matrix Multiplication
    D.-H. Park, S. Pal, S. Feng, P. Gao, J. Tan, A. Rovinski, S. Xie, C. Zhao, A. Amarnath, T. Wesley, J. Beaumont, K.-Y. Chen, C. Chakrabarti, M. Taylor, T. Mudge, D. Blaauw, H.-S. Kim and R. Dreslinski
    IEEE Journal of Solid State Circuits, 55(4), pp. 933-944, 2020.

  7. Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration
    S. Pal, S. Feng, D.-H. Park, S. Kim, A. Amarnath, C.-S. Yang, X. He, J. Beaumont, K. May, Y. Xiong, K. Kaszyk, M. Morton, J. Sun, M.O'Boyle, M. Cole, C. Chakrabarti, D. Blaauw, H.-S. Kim, T. Mudge and R. Dreslinski
    Proc. of 29th Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), Oct 2020.

  8. Compressing LSTM Networks with Hierarchical Coarse-grained Sparsity
    D. Kadetotad, J. Meng, V. Berisha, C. Chakrabarti and J.-S. Seo
    Proc. of INTERSPEECH, Oct 2020.

  9. Communications an dHigh-precision Positioning (CHP2): Enabling Secure CNS and APNT for Safety-critical Air Transport Systems
    S. Srinivas, A. Herschfelt, H. Yu, S. Wu, Y. Li, H. Lee, C. Chakrabarti and D.W. Bliss
    Proc. of IEEE/AIAA 38th Digital Avionics Systems Conference (DASC), 2020.

  10. Defending and Harnessing the Bit-Flip based Adversarial Weight Attack
    A.S. Rakin, Z. He, J. Li, C. Chakrabarti and D. Fan
    Conference on Computer Vision and Pattern Recognition (CVPR), June 2020.

  11. Defending Bit-Flip Attacks through DNN Weight Reconstruction
    J. Li, A.S. Rakin, Y. Xiong, L. Chang, Z. He, D. Fan and C. Chakrabarti
    Proc. of Design Automation Conference (DAC), June 2020.

  12. Accelerating Deep Neural Neytwork Computations on a Low Power Reconfigurable Architecture
    Y. Xiong, J. Zhou, S. Pal, D. Blaauw, H.-S. Kim, T. Mudge, R. Dreslinski and C. Chakrabarti
    Proc. of IEEE Symposium on Circuits and Systems (ISCAS), Oct 2020.

  13. Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture
    A. Soorishetty, J. Zhou, S. Pal, D. Blaauw, H.-S. Kim, T. Mudge, R. Dreslinski and C. Chakrabarti
    Proc. of IEEE Conf. on Acoustics, Speech and Signal Processing (ICASSP), May 2020.

2019

  1. Articulation Constrained Learning Application to Speech Emotion Recognition
    M. Shah, M. Tu, V. Berisha, C. Chakrabarti and A. Spanias
    EURASIP Journal on Audio, Speech and Music Processing, accepted for publication, 2019.

  2. Low Complexity Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low Power Mobile Vision Applications
    Z. Li, J. Xiang, L. Gong, D. Blaauw, C. Chakrabarti and H.-S. Kim
    IEEE Transactions on Circuits and Systems for Video Technology, 29(7), pp. 2191-2204, July 2019.

  3. MAX2: An ReRAM-based Neural Accelerator that Maximizes Data Reuse and Area Utilization
    M. Mao, X. Peng, R. Liu, J. Li, S. Yu and C. Chakrabarti
    IEEE Journal of Emerging Technologies, Circuits and Systems, 9(2), pp. 398-410, June 2019.

  4. A Deep Q-Learning Approach to Dynamic Management of Heterogeneous Processors
    U. Gupta, S. K. Mandal, M. Mao, C. Chakrabarti and U. Y. Ogras
    IEEE Computer Architecture Letters, 18(1), pp. 14-17, 2019.

  5. Configurable-ECC: Architecting a Flexible ECC Scheme to Support Different Sized Accesses in High Bandwidth Memory Systems
    H.-M. Chen, S.-Y. Lee, T.N. Mudge, C.-J. Wu and C. Chakrabarti
    IEEE Transactions on Computers, 68(5), pp. 646-659, May 2019.

  6. Delay Compression: Reducing Delay Calculation Requirements for 3D Plane-Wave Ultrasound
    B. West, J. Zhou. C. Chakrabarti and T. F. Wenisch
    Proc. of IEEE Ultrasound Symposium, Oct 2019.

  7. Improving Reliability of ReRAM-based DNN Implementation through Novel Weight Distribution
    J. Li, M. Mao and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, Oct 2019.

  8. Residual+Capsule Networks (ResCap) for Simultaneous Single-Channel Overlapped Keyword Recognition
    Y. Xiong, V. Berisha and C. Chakrabarti
    Proc. of INTERSPEECH, Sep 2019.

  9. Joint Positioning and Communications System Design and Experimental Demonstration
    A. Herschfelt, H. Yu, S. Yu, S. Srinivas, Y, Li, N. Sciammelta, L. Smith, K. Reuger, H. Lee, C. Chakrabarti and D. Bliss
    Proc. of IEEE/AIAA 38th Digital Avionics Systems Conference, 2019.

  10. A 7.3 M Output Non-Zeros/J Sparse matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40nm
    S. Pal, D.-H. Park, S. Feng, P. Gao, J. Tan, A. Rovinski, S. Xie, X. Zhao, A. Amarnath, T. Wesley, J. Beaumont, K.-Y. Chen, C. Chakrabarti, M. Taylor, T. Mudge, D. Blaauw, H.-S. Kim and R. Dreslinski
    Proc. of IEEE VLSI Symposia on VLSI Technology and Circuits, June 2019.

  11. Tetris: A Streaming Accelerator for Physics-Limited 3D Plane-Wave Ultrasound Imaging
    B. West, J. Zhou, C. Chakrabarti and T. F. Wenisch
    Proc. of Design Automation Conference, June 2019.

  12. Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks
    G. Srivastava, D. Kadetotad, S. Yin, V. berisha, C. Chakrabarti and J. Seo
    Proc. of IEEE Int. Conf. on Acoustics, Speech and Signal Processing, May 2019.

2018

  1. High Volume-rate 3D Ultrasound Imaging based on Synthetic Aperture Sequential Beamforming with Chirp-coded Excitation
    J. Zhou, S. Wei, R. Jintamethasawat, R. Sampson, O. Kripfgans, J. B. Fowlkes, T. F. Wenisch and C. Chakrabarti
    IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, pp. 1346-1358, Aug 2018.

  2. Error Analysis of Speed of Sound Reconstruction in Ultrasound Limited Angle Transmission Tomography
    R. Jintamethasawat, W.-M. Lee, P. L. Carson, F. M. Hooi, J. B. Fowlkes, M. M. Goodsitt, R. Sampson, T. F. Wenisch, S. Wei, J. Zhou, C. Chakrabarti and O. Kripfgans
    Ultrasonics, 88, pp. 174-184, 2018.

  3. Design and Analysis of Energy-efficient and Reliable 3D ReRAM Cross-point Array System
    M. Mao, S. Yu and C. Chakrabarti
    IEEE Transactions on VLSI Systems, pp. 1290-1300, July 2018.

  4. Reducing Energy of Baseband Processor for IoT Terminals with Long Range Wireless Communication
    S. Wu, C. Chakrabarti and H. Lee
    Journal of Signal Processing Systems, pp, 1345-1355, Aug 2018.

  5. A Versatile ReRAM-based Accelerator for Convolutional Neural Networks
    M Mao, X. Sun, X. Peng, S. Yu and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, Oct 2018.

  6. A Parallel RRAM Synaptic Array Architecture for Energy-efficient Recurrent Neural Networks
    S. Yin, X. Sun, S. Yu, J.-S. Seo and C. Chakarbarti
    Proc. of IEEE Workshop on Signal Processing Systems, Oct 2018.

  7. Parallel Wavelet-based Bayesian Compressive Sensing based on Gibbs Sampling
    J. Zhou and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, Oct 2018.

  8. Synthetic Aperture Vector Flow Imaging with Specle Tracking
    S. Wei, J. Zhou, O. D. Kripfgans, J. B. Fowlkes, T. F. Wenisch and C. Chakrabarti
    Proc. of IEEE Ultrasound Symposium, Oct 2018.

  9. OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator
    S. Pal, J. Beaumont, D.-H. Park, A. Amarnath, S. Feng, C. Chakrabarti, H.-S. Kim, D. Blaauw, T. Mudge and R. Drelinski
    Proc. of High Performance Computer Architecture, pp. 724-736, March 2018.

2017

  1. Low-Cost 3-D Flow Estimation of Blood with Clutter
    S. Wei, M. Yang, J. Zhou, R. Sampson, O. Kripfgans, J.B. Fowlkes, T.F. Wenisch and C. Chakrabarti
    IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, 64(5), March 2017.

  2. A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Crosspoint Array System
    M. Mao, P.-Y. Chen, S. Wu and C. Chakrabarti
    IEEE Transactions on VLSI Systems, 25(5), 2017.

  3. Cost Effective Design Solutions for Enhancing PRAM Reliability and Performance
    C. Yang, M. Mao, Y. Cao and C. Chakrabarti
    IEEE Transactions on Multi-Scale Computing Systems, 3(1), 2017.

  4. A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware
    M. Shah, S. Arunachalam, J. Wang, D. Blaauw, D. Sylvester, H.-S. Kim, J. Seo and C. Chakrabarti
    Journal of Signal Processing Systems, Spring 2017 (online version in Nov 2016).

  5. Minimizing Area and Energy of Deep Learning Hardware Design using Collective Low Precision and Structured Compression
    S. Yin, G. Srivastava, S. K. Venkataramanaiah, C. Chakrabarti, V. Berisha and J. Seo
    Asilomar Conference on Signals, Systems and Computers, November 2017.

  6. Fluid Wireless Protocols: Energy-Efficient Design and Implementation
    G. Bhat, S. Srinivas, V. Chagari, J. Park, T. McGiffen, H. Lee, D. W. Bliss, C. Chakrabarti and U. Ogras
    IEEE/ACM Symposium in Embedded Systems for Multimedia (ESTIMedia), October 2017.

  7. Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks based on Back Propagation with Binary Activations
    S. Yin, S. K. Venkataramanaiah, G. K. Chen, R. Krishnamurthy, Y. Cao, C. Chakrabarti and J. Seo
    IEEE Biomedical Circuits and Systems Conference (BioCAS), October 2017.

  8. High Volume Rate 3D Ultrasound Imaging using Synthetic Aperture Sequential Beamforming
    J. Zhou, S. Wei, R. Sampson, R. Jinthamethasawat, O. Kripfgans, J. B. Fowlkes, T. F. Wenisch and C. Chakrabarti
    IEEE Ultrasonics Symposium (IUS), October 2017.

  9. Low Power Neuromorphic Speech Recognition Engine with Coarse-grain Sparsity
    S. Yin, D. Kadetotad, B. Yan, C. Song, Y. Chen. C. Chakrabarti and J. Seo
    Asia and South Pacific Design Automation Conference (ASp-DAC), January 2017.

2016

  1. RATT-ECC: Rate-Adaptive Two-Tiered Error Correction Codes for Reliable 3D Die-Stacked Memories
    H.-M. Chen, C.-J. Wu, T. Mudge and C. Chakrabarti
    ACM Transactions on Architectures and Code Optimization, 13(3), September 2016.

  2. Using Low Cost Erasure and Error Correction Schemes to Improve Reliability of Commodity DRAM Systems
    H.-M. Chen, S. Jeloka, A. Arunkumar, D. Blaauw, C.-J. Wu, T. Mudge and C. Chakrabarti
    IEEE Transactions on Computers, 65(12), April 2016.

  3. Optimizing Latency, Energy and Reliability of 1T1R ReRAM through Cross-Layer Techniques
    M. Mao, Y. Cao, S. Yu and C. Chakrabarti
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems; Special issue on Emerging Memories, 6(3), 2016.

  4. Low Power Baseband Processor for IoT Terminals with Long Range Wireless Communications
    S. Wu, S. Kang, C. Chakrabarti and H. Lee
    Global Conference on Signal and Information Processing (GlobalSIP), Dec 2016.

  5. Efficient Memory Compression in Deep Neural Networks using Coarse-Grain Sparsification for Speech Applications
    D. Kadetotad, S. Arunachalam, C. Chakrabarti and J. Seo
    IEEE Int. Conf. on Computer Aided Design, Nov 2016.

  6. Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low Power Vision Applications
    J. Xiang, Z. Li, H.-S. Kim and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, Oct 2016. Best Paper Award.

  7. Low Complexity 3D Ultrasound Imaging using Synthetic Aperture Sequential Beamforming
    J. Zhou, S. Wei, R. Sampson, R. Jintamethasawat, O. Kripfgans, J.B. Fowlkes, T. F. Wenisch and C. Chakrabarti
    Proc. of IEEE Ultrasonicsc Symposium, Oct 2016.

  8. Improving Plane Wave Imaging Performance through Post-Processing
    S. Wei, J. Zhou, R. Sampson, R. Jintamethasawat, O. Kripfgans, J.B. Fowlkes, T. F. Wenisch and C. Chakrabarti
    Plane Wave Imaging Challenge in Medical Ultrasound (PICMUS), Proc. of IEEE Ultrasonics Symposium, Oct 2016.

  9. Checkpointing Exascale Memory Systems with Existing Memory Technologies
    N. Abeyratne, H.-M. Chen, B. Oh, R. Dreslinksi, C. Chakrabarti and T. Mudge
    Proc. of Int. Symp. on Memory Systems (MEMSYS), Oct 2016.

  10. Low Complexity Optical Flow using Neighbor-Guided Semi-Global Matching
    J. Xiang, Z. Li, D. Blaauw, H.-S. Kim and C. Chakrabarti
    Proc. of Int. Conf. on Image Processing, Sep 2016.

  11. Design of a Reliable RRAM-based PUF for Compact Hardware Security Primitives
    A. Shrivatsava, P.-Y.Chen, Y. Cao, S. Yu and C. Chakrabarti
    Proc. of Int. Symp. on Circuits and Systems, May 2016.

2015

  1. Within and Cross Corpus Speech Emotion Recognition using Latent Topic Model-based Functions
    M. Shah, C. Chakrabarti and A. Spanias
    EURASIP Journal on Audio, Speech and Music Processing, 2015:4(2015).

  2. Separable Beamforming for 3-D Medical Ultrasound Imaging
    M. Yang, R. Sampson, S. Wei, T. F. Wenisch and C. Chakrabarti
    IEEE Transactions on Signal Processing, 63(2): 279-290, Feb 2015.

  3. An Overview of Recent Advances in Distributed and Agile Sensing Algorithms and Implementations
    M. K. Banaver, J. J. Zhang, B. Chakraborty, H. Kown, Y. Li, H. Jiang, A. Spanias, C. Tepedenlenlioglu, C. Chakrabarti and A, Papandreou-Suppappola
    Digital Signal Processing, vol 39, pp. 1-14, 2015.

  4. Using Graphics Processing Units in an LTE Basestation
    Q. Zheng, Y. Chen, H. Lee, R. G. Dreslinski, C. Chakrabarti, A. Anastapoulos, S. A. Mahlke and T. N. Mudge
    Journal of Signal Processing Systems, 78(1): 35-47, 2015.

  5. High Frame Rate 3-D Ultrasound Imaging Using Separable Beamforming
    M. Yang, R. Sampson, S. Wei, T. F. Wenisch and C. Chakrabarti
    Journal of Signal Processing Systems, 78(1): 73-84, 2015.

  6. Optimizing Latency, Energy and Reliability of 1T1R ReRAM through Appropriate Voltage Settings
    M. Mao, Y. Cao, S. Yu and C. Chakrabarti
    Proc. of Int. Conf. on Computer Design, pp. 388-395, Oct 2015.

  7. E-ECC: Low Power Erasure and Error Correction Schemes for Increasing Reliability of Commodity DRAM Systems
    H.-M. Chen, A. Arunkumar, C.-J. Wu. T. Mudge and C. Chakrabarti
    Proc. of Int. Symp. on Memory Systems (MEMSYS), pp. 60-70, Oct 2015.

  8. Programming Strategies to Improve Energy Efficiency and Reliability of ReRAM Memory Systems
    M. Mao, Y. Cao, S. Yu and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, Oct 2015.

  9. Low Cost Clutter Filter for 3D Ultrasonic Flow Estimation
    S. Wei, M. Yang, R. Sampson, O. Krifgans, J. B. Fowlkes, T. F. Wenisch and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, Oct 2015.

  10. A Fixed-point Neural Network for Keyword Detection in Resource Constrained Hardware
    M. Shah, J. Wang, D. Blaauw, D. Sylvester, H.-S. Kim and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, Oct 2015.

  11. FPGA Implementation of Low Power 3D Ultrasound Beamformer
    R. Sampson, M. Yang, S. Wei, R. Jintamethaswat, J. B. Fowlkes, O. Kripfgans, C. Chakrabarti and T. F. Wenisch
    Proc. of IEEE Ultrasonics Symposium, Oct 2015.

  12. Exploiting Resistive Cross-point Array for Compact Design of Physical Unclonable FUnctions
    P. Y. Chen, R. Fang, R. Lui, C. Chakrabarti and S. Yu
    Proc. of Hardware-Oriented Security and Trust (HOST), pp. 36-31, 2015.

2014

  1. Sonic Millip3De: An Architecture for Handheld 3D Ultrasound
    R. Sampson, M. Yang, S. Wei, C. Chakrabarti and T. F. Wenisch
    IEEE Micro Top Picks, 34(3): 100-108, March 2014.

  2. A Distributed Canny Edge Detector: Algorithm and FPGA Implementation
    Q. Xu, S. Varadarajan, C. Chakrabarti and L. J. Karam
    IEEE Trans on Image Processing, 23(7): 2944-2960, July 2014.

  3. A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell PRAM
    C. Yang, Y. Emre, Z. Xu, H.-M. Chen, Y. Cao and C. Chakrabarti
    Journal of Signal Processing Systems, 76(2): 225-234, 2014.

  4. Improving the Reliability of MLC NAND Flash Memories through Adaptive Data Refresh and Error Control Coding
    C. Yang, H.-M. Chen, T. N. Mudge and C. Chakrabarti
    Journal of Signal Processing Systems, 76(3): 225-234, 2014.

  5. Compact Modeling of STT-MTJ Devices
    Z. Xu, C. Yang, M. Mao, K. Sutaria, C. Chakrabarti and Y. Cao
    Solid State Electronics, vol 102, pp.76-81, Dec 2014.

  6. A Low Complexity Scheme for Accurate 3D Velocity Estimation in Ultrasound Systems
    S. Wei, M. Yang, C. Chakrabarti, R. Sampson, T. F. Wenisch, O. Kripfgans and J. B. Fowlkes
    Proc. of IEEE Workshop on Signal Processing Systems, pp. 85-90, 2014.

  7. Low Cost ECC Schemes for Improving the Reliability of DRAM+PRAM Main Memory Systems
    M. Mao, X. Yang, Z. Xu, Y. Cao and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, pp. 139-144, 2014.

  8. High Volume Rate, High Resolution 3D Plane Wave Imaging
    M. Yang, R. Sampson, S. Wei, T. F. Wenisch, J. B. Fowlkes, O. Kripfgans and C. Chakrabarti
    Proc. of IEEE Ultrasonics Symposium, Sep 2014.

  9. A Hybrid Approach to Offloading Mobile Image Classification
    J. Hauswald, T. Manville, Q. Zheng, R. G. Dreslinski, C. Chakrabarti and T. N. Mudge
    Proc. of Int. Conf. on Acoustics, Speech and Signal Processing, pp. 8375-8379, 2014.

  10. A Multi-modal Approach to Emotion Recognition using Undirected Topic Models
    M. Shah, C. Chakrabarti and A. S. Spanias
    Proc. of Int. Symp. on Circuits and Systems, pp. 754-757, 2014.

  11. Image Processing Using Approximate Datapath Units
    M. Vasudevan and C. Chakrabarti
    Proc. of Int. Symp. on Circuits and Systems, pp. 1544-1547, 2014.

2013

  1. Energy and Quality-Aware Multimedia Signal Processing
    Y. Emre and C. Chakrabarti
    IEEE Trans on Multimedia, Nov 2013.

  2. Efficient Bayesian Tracking of Multiple Sources of Neural Activity: Algorithms and Real-Time FPGA Implementation
    L. Miao, J. J. Zhang, C. Chakrabarti and A. Papandreou-Suppappola.
    IEEE Trans on Signal Processing, March 2013.

  3. Multi-source Neural Activity Estimation and Sensor Scheduling: Algorithms and Hardware Implementation
    L. Miao, S. Michael, N. Kovvali, C. Chakrabarti and A. Papandreou-Suppappola.
    Journal of Signal Processing Systems, (invited paper).

  4. Hardware Acceleration for Neuromorphic Vision Algorithms
    A. Al Maashri, M. Cotter, N. Chadramoorthy, M. DeBole, C.-L. Yu, V. Narayanan and C. Chakrabarti
    Journal of Signal Processing Systems, (invited paper).

  5. Techniques for Compensating Memory Errors in JPEG2000
    Y. Emre and C. Chakrabarti.
    IEEE Trans on VLSI Systems, Jan 2013.

  6. Exploring DRAM Optimizations for Energy-Efficient and Resilient Exascale Memories
    B. Giridhar, M. Cieslak, D. Duggal, H.-M. Chen, R. Dreslinksi, R. Patti, B. Hold, C. Chakrabarti, T. Mudge and D. Blaauw
    Proc. of Supercomputing Conference, Nov 2013.

  7. Separable Beamforming for 3D Synthetic Aperture Ultrasound Imaging
    M. Yang, R. Sampson, T. F. Wenisch and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, Oct 2013.

  8. A Parallel Stochastic Computing System with Improved Accuracy
    L. Miao and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, Oct 2013.

  9. Architecting an LTE Basestation with Graphics Processing Units
    Q. Zheng, Y. Chen, R. Dreslinksi, C. Chakrabarti, A. Anastasopoulos, S. Mahlke and T. Mudge
    Proc. of IEEE Workshop on Signal Processing Systems, Oct 2013.

  10. Compact Modeling of STT-MTJ for SPICE Simulation
    Z. Xu, K. B. Sutaria, C. Yang, C. Chakrabarti and Y. Cao
    Proc. of the European Solid State Device Research and Circuits Conference.

  11. WiBench: An Open Source Kernel Suite for Benchmarking Wireless Systems
    Q. Zheng, Y. Chen, R. Dreslinksi, C. Chakrabarti, A. Anastasopoulos, S. Mahlke and T. Mudge
    Proc. of Int. Symp. on Workload Characterization, Sep 2013.

  12. Sonic Millip3De with Dynamic Receive Focusing and Apodization Optimization
    R. Sampson, M. Yang, S. Wei, C. Chakrabarti and T. F. Wenisch
    Proc. of IEEE Ultrasound Symposium, July 2013.

  13. Data Storage Time Sensitive ECC Schemes for MLC NAND Flash Memories
    C. Yang, D. Muckatira, A. Kulkarni and C. Chakrabarti
    Proc. of Int. Conf. on Acoustics, Speech and Signal Processing, May 2013.

  14. A Speech Emotion Recognition Framework based on Latent Dirichlet Allocation: Algorithm and FPGA Implementation
    M. Shah, L. Miao, C. Chakrabarti and A. Spanias
    Proc. of Int. Conf. on Acoustics, Speech and Signal Processing, May 2013.

  15. Parallelization Techniques for Implementing Trellis Algorithms on Graphics Processors
    Q. Zheng, Y. Chen, R. Dreslinski, C. Chakrabarti, A. Anastasopoulos, S. Mahlke and T. Mudge
    Proc. of Int. Symp. on Circuits and Systems, May 2013.

  16. Sonic Millip3De: A Massively Parallel 3D-Stacked Accelerator for 3D Ultrasound
    R. Sampson, M. Yang, S. Wei, C. Chakrabarti and T. F. Wenisch
    Proc. of High Performance Computer Architecture, Feb 2013, Best Paper Award.

2012

  1. Product Code Schemes for Error Correction in MLC NAND Flash Memories
    C. Yang, Y. Emre and C. Chakrabarti.
    IEEE Trans. on VLSI Systems, Dec 2012.

  2. Improving Reliability of Non-Volatile Memory Technologies through Circuit-Level Techniques and Error Control Coding
    C. Yang, Y. Emre, Y. Cao and C. Chakrabarti
    Eurasip Journal on Advances in Signal Processing, Sep 2012.

  3. A Super-Pipelined Energy Efficient Subthreshold 240MS/s FFT Core in 65nm CMOS
    D. Jeon, M. Seok, C. Chakrabarti, D. Blaauw and D. Sylvester.
    Journal of Solid State Circuits, Jan 2012.

  4. Parallel High Throughput Soft-Output Sphere Decoding Algorithm
    Q. Qi and C. Chakrabarti.
    Journal of Signal Processing Systems, 68(2), 2012.

  5. Quality-Aware Techniques for Reducing Power of JPEG Codecs
    Y. Emre and C. Chakrabarti.
    Journal of Signal Processing Systems, 69(3), 2012. (invited paper).

  6. Hierarchical Modeling of Phase Change Memory for Reliable Design
    Z. Xu, K. Sutaria, C. Yang. C. Chakrabarti and Y. Cao.
    Proc. of the Int. Conf. on Computer Design, 2012.

  7. EEG/MEG Artifact Suppression for Improved Neural Activity Estimation
    A. Maurer, L. Miao, J. J. Zhang, N. Kovvali, A. Papandreou-Suppappola and C. Chakrabarti.
    Asilomar Conference on Signals, Systems and Computers, Nov 2012.

  8. Enhancing the Reliability of STT-RAM through Circuit and System-level techniques
    Y. Emre, C. Yang, K. Sutaria, Y. Cao and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2012.

  9. A Multi-tiered Approach to Improving the Reliability of Multi-level Cell PRAM
    C. Yang, Y. Emre, Y. Cao and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2012.

  10. Reducing the Complexity of Orthogonal Code-based Synthetic Aperture Ultrasound System
    M. Yang, S. Wei and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2012.

  11. Process Variation in Near-Threshold Wide SIMD Architectures
    S. Seo, R. G. Dreslinski, M. Woh, Y. Park, C. Chakrabarti, S. Mahlke, D. Blaauw and T. Mudge.
    Proc. of Design Automation Conference, June 2012.

  12. Accelerating Neuromorphoc Vision Algorithms for Recognition
    A. Al Maashri, M. Debole, M. Cotter, N. Chandramoorthy, Y. Xiao, C. Chakrabarti and V. Narayanan.
    Proc. of Design Automation Conference, June 2012.

  13. Design of Orthogonal Coded Excitation for Synthetic Aperture Imaging in Ultrasound Systems
    M. Yang and C. Chakrabarti.
    Proc. of Int. Symp. on Circuits and Systems, May 2012.

  14. Transpose-free SAR Imaging on FPGA Platform
    C.-L Yu and C. Chakrabarti.
    Proc. of Int. Symp. on Circuits and Systems, May 2012.

  15. Neural Activity Tracking using Spatial Compressive Particle Filtering
    L. Miao, J. J. Zhang, A. Papandreou-Suppappola and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, April 2012.

  16. A Top-Down Design Methodology using Virtual Platforms for Concept Development
    M Shah, B. Mears, C. Chakrabarti and A. Spanias.
    Proc. of Int. Symp. on Quality Electronic Design, March 2012.

  17. An Analytical Approach for Efficient Circuit Variability Analysis in Scaled CMOS Design
    S. Gummalla, A. R. Subramaniam, Y. Cao and C. Chakrabarti.
    Proc. of Int. Symp. on Quality Electronic Design, March 2012.

2011

  1. Algorithm and Parallel Implementation of Particle Filtering and its Use in Waveform-Agile Sensing
    L. Miao, J. J. Zhang, C. Chakrabarti and A. Papandreou-Suppappola.
    Journal of Signal Processing Systems, Dec 2011 (invited paper).

  2. Multi-dimensional DFT IP Generator for FPGA Platforms
    C.-L. Yu, K. Irick, C. Chakrabarti and V. Narayanan.
    IEEE Trans on Circuits and Systems I, April 2011.

  3. FPGA Architecture for 2D Discrete Fourier Transform based on 2D Decomposition for Large Sized Data
    C.-L. Yu, J. S. Kim, L. Deng, S. Kestur, V. Narayanan and C. Chakrabarti.
    Journal of Signal Processing Systems, Spring 2011.

  4. A Framework for Accelerating Neuromorphic Vision Algorithms on FPGA
    M. debole, A. Al Maashri, M. Cotter, C.-L. Yu, C. Chakrabarti and V. Narayanan.
    Proc. of the International Conference on Computer-Aided Design, Nov 2011.

  5. A Hardware Architecture for Accelerating Neuromorphic Vision Algorithms
    A. Al Maashri, M. Debole, C.-L. Yu, C. Chakrabarti and V. Narayanan.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2011.

  6. Flexible Product Code-based ECC Schemes for MLC NAND Flash Memories
    C. Yang. Y. Emre, C. Chakrabarti and T. Mudge.
    Proc. of the IEEE Workshop in Signal Processing Systems, Oct 2011.

  7. Real-Time Closed-Loop Tracking of an Unknown Number of Neural Sources using probability Hypothesis Density Particle Filtering
    L. Miao, J. J. Zhang, C. Chakrabarti, A. Papandreou-Suppappola and N. Kovvali.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2011. (Student Best Paper Award Finalist).

  8. Low Energy Motion Estimation via Selective Approximation
    Y. Emre and C. Chakrabarti.
    Proc. of the IEEE Int. Conf. on Application-specific Systems, Architectures and Processors, Sep 2011.

  9. A 0.27V, 30MHz, 17.7nJ/transform 1024-pt Complex FFT Core with Super-pipelining
    M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw and D. Sylvester.
    Proc. of the International Solid State Circuits Conference, Feb 2011.

  10. Energy-optimized High Performance FFT Processor
    M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw and D. Sylvester.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, June 2011.

  11. Datapath and Memory Error Compensation Techniques for Low Power JPEG Implementations
    Y. Emre and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, June 2011.

  12. Pipeline Strategy for Improving Optimal Energy Efficiency in Ultra Low Voltage Design
    M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw and D. Sylvester.
    Proc. of the Design Automation Conference, June 2011.

  13. An Algorithm-Architecture Co-design Framework for Gridding Reconstruction using FPGAs
    S. Kestur, K. Irick, S. Park, A. Al Mashri, V. Narayanan and C. Chakrabarti.
    Proc. of the Design Automation Conference, June 2011.

2010

  1. Random Variability Modeling and its Impact on Scaled CMOS Circuits
    Y. Ye, S. Gummalla, C.-C. Wang, C. Chakrabarti and Y. Cao.
    Journal of Computational Electronics, Dec 2010.

  2. Accurate Area, Time and Power Models for FPGA-based Implementations
    L. Deng, K. Sobti, Y. Zhang and C. Chakrabarti.
    Journal of Signal Processing Systems, Spring 2010.

  3. A Low Power DSP for Wireless Communications
    H. Lee, C. Chakrabarti and T. Mudge.
    IEEE Trans on VLSI Systems, Sep 2010.

  4. AnySP: Anytime Anywhere Anyway Signal Processing
    M. Woh, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti and K. Flautner.
    IEEE MICRO Top Picks, Jan/Feb 2010.

  5. Mobile Supercomputer for the Next Generation Cell Phone
    M. Woh, S. Mahlke, T. Mudge and C. Chakrabarti.
    IEEE Computer, Jan 2010.

  6. Multiple Sensor Sequential Tracking of Neural Activity: Algorithm and FPGA Implementation
    L. Miao, J. J. Zhang, C. Chakrabarti and A. Papandreou-Suppappola.
    Proc. of the Asilomar Conference on Signals, Systems and Computers, Nov 2010.

  7. An Ultra Low Power SIMD Processor for Wireless Devices
    M. Woh, S. Seo, C. Chakrabarti, S. Mahlke and T. Mudge.
    Proc. of the Asilomar Conference on Signals, Systems and Computers, Nov 2010.

  8. A New Parallel Implementation for Particle Filters and its Applications to Adaptive Waveform Design
    L. Miao, J. J. Zhang, C. Chakrabarti and A. Papandreou-Suppappola.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2001. Best Paper Award.

  9. Memory Error Compensation Techniques for JPEG2000
    Y. Emre and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2010.

  10. Parallel Deblocking Filter for H.264 AVC/SVC
    V. Sundaram and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2010.

  11. Parallel High Throughput Soft-Output Sphere Decoder
    Q. Qi and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2010.

  12. Diet-SODA: A Power-Efficient Processor for Digital Cameras
    S. Seo, R. Dreslinski, M. Woh, C. Chakrabarti, S. Mahlke and T. Mudge.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Aug 2010.

  13. Energy-aware OFDM Systems
    Y. Emre and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, March 2010.

  14. Bandwidth-intensive FPGA Architectures for Multi-dimensional DFT
    C.-L. Yu, C. Chakarabarti, S. Park and V. Narayanan.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, March 2010.

  15. A Distributed Psycho-Visually Motivated Canny Edge Detector
    S. Varadarajan, C. Chakrabarti, L. J. Karam and J. M. Bauza.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, March 2010.

  16. A Special-purpose Compiler for Look-up Table and Code Generation for Function Evaluation
    Y. Zhang, L. Deng, P. Yedlapalli, S. Muralidharan, H. Zhao. M. Kandemir, C. Chakrabarti, N. Pitsianis and X. Sun.
    Proc. of Design and Test in Europe, March 2010.

2009

  1. An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms using Algorithmic/Architectural Optimization
    J. S. Kim, L. Deng, P. Mangalagiri, K. Irick, K. Sobti, M. Kandemir, V. Narayanan, C. Chakrabarti, N. Pitsianis and X. Sun.
    IEEE Trans on Computers, Dec 2009.

  2. Architecture-Aware LDPC Code Design for Multi-Processor Software Defined Radio Systems
    Y. Zhu and C. Chakrabarti.
    IEEE Trans on Signal Processing, Sep 2009.

  3. Design Methodology for Low Power Dissipation and Parametric Robustness through Output Quality Modulation: Application to Color Interpolation Filtering
    N. Banerjee, G. Karkaonstantis, J. H. Choi, C. Chakrabarti and K. Roy.
    IEEE Trans on Computer Aided Design, August 2009.

  4. Energy Efficient Video Transmission over a Wireless Link
    Y. Li, M. Reisslein and C. Chakrabarti.
    IEEE Trans on Vehicular Technology, March 2009.

  5. Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids
    J. Zhuo, C. Chakrabarti, K. Lee, N. Chang and S. Vrudhula.
    IEEE Trans on VLSI Systems, Jan 2009.

  6. An H.264/SVC Memory Architecture Supporting Spatial and Coarse-Grained Quality Scalabilities
    N. Narvekar, B. Konnanath, S. Mehta, S. Chintalapati, J. AlKamal, C. Chakrabarti and L. Karam.
    Proc. of the Int. Conf. on Image Processing, Nov 2009.

  7. FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-Sized Data
    J. S. Kim, C. _L. Yu, L. Deng, S. Kestur, V. Narayanan and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2009.

  8. Automated Optimization of Look-Up Table Implemenaations for Function Evaluation on FPGAs
    L. Deng, C. Chakrabarti, N. Pitsianis and X. Sun.
    Proc. of SPIE vol. 8444, Aug 2009.

  9. Low Power Robust Signal Processing
    V. Papirla, A. Jain and C. Chakrabarti.
    Proc. of the Int. Symp. on Low Power Electronics and Design, July 2009.

  10. Energy-aware Error Control Coding for Flash Memories
    V. Papirla and C. Chakrabarti.
    Proc. of the IEEE/ACM Design Automation Conference, July 2009.

  11. AnySP: Anytime Anywhere Anyway Signal Processing
    M. Woh, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti and K. Flautner.
    Proc. of the International Symposium on Computer Architecture, June 2009.

2008

  1. Energy-efficient Dynamic Task Scheduling for DVS Systems
    J. Zhuo and C. Chakrabarti.
    ACM Transactions on Embedded Computing Systems, Feb 2008.

  2. A Fuel Cell-Battery Hybrid for Portable Embedded Systems
    K. Lee, N. Chang, J. Zhuo, C. Chakrabarti, S. Kadri and S. Vrudhula.
    ACM Transactions on Design Automation of Embedded Systems, Jan 2008.

  3. From SODA to Scotch: The Evolution of a Wireless Baseband Processor
    M. Woh, Y. Lin, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti, R. Bruce, D. Kershaw, A. Reid, M. Wilder and K. Flautner.
    Proc. of the IEEE/ACM International Symposium on Microarchitecture, Nov 2008. Best Paper Award.

  4. Efficient Mapping of Advanced Signal Processing Algorithms on MultiprocessorArchitectures
    B. Manjunath, A. Williams, C. Chakrabarti and A. Papandreou-Suppappola.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2008.

  5. Efficient Image Reconstruction using Partial 2D Fourier Transform
    L. Deng, C.-L. Yu, C. Chakrabarti, J. Kim and V. Narayanan.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2008.

  6. Extending the Lifetime of Media Recorders Constrained by Battery and Flash Memory Size
    Y. Kim, Y. Cho, N. Chang, C. Chakrabarti and N. I. Cho.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Aug 2008.

  7. A Parameterized Dataflow Language Extension for Embedded Streaming Systems
    Y. Lin, Y. Choi, S. Mahlke, T. Mudge and C. Chakrabarti.
    Proc. of the Int. Symp. on Systems, Architectures, Modeling and Simulation, July 2008.

  8. Accurate Models for Estimating Area and Power of FPGA Implementations
    L. Deng, K. Sobti and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, April 2008.

2007

  1. SODA: A High-Performance DSP Architecture for Software Defined Radio
    Y. Lin, H. Lee, M. Woh, S. Mahlke, T. Mudge, Y. Harel, C. Chakrabarti and K. Flautner.
    MICRO Top Picks, Jan/Feb 2007.

  2. Automatic Antenna-Tuning Unit for Software-Defined and Cognitive Radio
    S.-H. Oh, H. Song, J. Aberle, B. Bakkaloglu and C. Chakrabarti.
    Wireless Communications and Mobile Computing Journal, 2007.

  3. A Comprehensive Energy Model and Energy-Quality Evaluation for Wireless Transceiver Front-Ends
    Y. Li, B. Bakkaloglu and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp. 90-103, Jan 2007.

  4. Design Methodology to Trade-Off Power, Output Quality and Error Resiliency: Application to Color Interpolation Filtering
    G. Karakonstantis, N. Banerjee, K. Roy and C. Chakrabarti.
    Proc. of the Int. Conf. on Computer Aided Design, Nov 2007.

  5. Sphere Decoding for Multiprocessor Architectures
    Q. Qi and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2007.

  6. Design and Analysis of LDPC Decoders for Software Defined Radio
    S. Seo, T. Mudge, Y. Zhu and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2007.

  7. Efficient Function Evaluations with Lookup tables for Structured Matrix Operations
    K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, X. Sun, J. Kim, P. Mangalgiri, V. Narayanan and M. Kandemir.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2007.

  8. Energy Management of DVS-DPM Enabled Embedded Systems Powered by Fuel Cell-Battery Hybrid Source
    J. Zhuo, C. Chakrabarti and N. Chang.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Aug 2007.

  9. Throughput of Multi-Core Processors under Thermal Constraints
    R. Rao, S. Vrudhula and C. Chakrabarti.
    Proc. of the Int. Int. Symp. on Low Power Electronics and Design, Aug 2007.

  10. TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform
    J. Kim, P. Mangalagiri, K. Irick, M. Kandemir, V. Narayanan, K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis and X. Sun.
    Proc. of the 17th Int. Conf. on Field Programmable Logic and Applications, Aug 2007.

  11. The Next Generation Challenge for Software Defined Radio
    M. Woh, S. Seo. H. Lee, Y. Lin, S. Mahlke, T. Mudge, C. Chakrabarti and K. Flautner.
    Proc. of the Int. Symp. on Systems, Architectures, Modeling and Simulation, July 2007. Best Paper Award.

  12. Dynamic Power Management with Hybrid Power Sources
    J. Zhuo, C. Chakrabarti, K. Lee and N. Chang.
    Proc. of the Design Automation Conference, June 2007.

  13. Memory Efficient LDPC Code Design for High Throughput Software Defined RadioSystems
    Y. Zhu and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, April 2007.

2006

  1. A Co-processor Architecture for Fast Protein Structure Prediction
    M. Marolia, R. Khoja, T. Acharya and C. Chakrabarti.
    Pattern Recognition, pp. 2494-2505, Dec 2006.

  2. A Survey of Lifting-Based Discrete Wavelet Transform Architectures
    T. Acharya and C. Chakrabarti.
    Journal of VLSI Signal Processing, pp. 321-329, March 2006.

  3. Study of Energy and Performance of Space-Time Decoding Systems in Concatenation with Turbo Decoding
    Y. Zhu, L. Li and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pg. 86-90, Jan 2006.
  4. Architecture-Aware LDPC Code Design for Software Defined Radio
    Y. Zhu and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2006.

  5. Design and Implementation of Turbo Decoders for Software Defined Radio
    Y. Lin, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner and A. Reid
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2006.

  6. Reducing Idle Mode Power in Software Defined Radio Terminals
    H. Lee, T. Mudge and C. Chakrabarti.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Oct 2006.

  7. An Optimal Analytical Solution for Processor Speed Control with Thermal Constraints
    R. Rao, S. Vrudhula, C. Chakrabarti and N. Chang.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Oct 2006.

  8. Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids
    J. Zhuo, C. Chakrabarti, N. Chang and S. Vrudhula.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Oct 2006.

  9. High-level Power Management of Embedded Systems with Application-Specific Energy Cost Function
    Y. Cho, N. Chang, C. Chakrabarti and S. Vrudhula.
    Proc. of the Design Automation Conference, July 2006.

  10. Extending the LIfetime of Fuel Cell Based Hybrid Systems
    J. Zhuo, C. Chakrabarti, N. Chang and S. Vrudhula.
    Proc. of the Design Automation Conference, July 2006.

  11. SODA: A Low Power Architecture for Software Radio
    Y. Lin, H. Lee, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti and K. Flautner.
    Proc. of the Int. Symp. on Computer Architecture, June 2006.

  12. Aggregated Circulant Matrix Based LDPC Codes
    Y. Zhu and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, May 2006.

2005

  1. An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits
    H. Rahman and C. Chakrabarti.
    IEEE Trans on Circuits and Systems II, August 2005.

  2. Memory Subbanking Schemes for High Throughput MAP based SISO Decoders
    M. Tiwari, Y. Zhu and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp, 494-498, April 2005.

  3. Static Task Scheduling Algorithm for Battery Powered DVS Systems
    P. Chowdhury and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp. 226-233, Feb 2005.

  4. Multi-port Memory Design for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti.
    Design Automation for Embedded Systems, vol. 9, pp. 235-261, 2005.

  5. A Comprehensive Energy Model and Energy-Quality Trade-offs for Wireless Transceiver Front-Ends
    Y. Li, B. Bakkaloglu and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Nov 2005.

  6. Battery Aware Wireless Ad-Hoc Routing Protocol
    Q. Qi and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Nov 2005.

  7. A Co-Processor Architecture for fast Protein Structure Prediction
    M. Marolia, R. Khoja, T. Acharya and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Nov 2005.

  8. System-Level Energy-Efficient Dynamic Task Scheduling Algorithms
    J. Zhuo and C. Chakrabarti.
    Proc. of the Design Automation Conference (DAC), June 2005.

  9. An Efficient Dynamic Task Scheduling Algorithm for Battery Powered DVS Systems
    J. Zhuo and C. Chakrabarti.
    Proc. of the Asia South Pacific Design Automation Conference (ASP-DAC), Jan 2005.

2004

  1. Design and Implementation of Low Energy Turbo Decoders
    J. Kaza and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp. 968-977, Sep 2004.

  2. Mobile Supercomputers
    T. Austin, D. Blaauw, S. Mahlke, T. Mudge, C. Chakrabarti and W. Wolf.
    IEEE Computer, pp. 81-83, May 2004.

  3. An Approach for Adaptively Approximating the Viterbi Algorithm to Reduce Power Consumption while Decoding Convolutional Codes
    R. Henning and C. Chakrabarti.
    IEEE Transactions on Signal Processing, pp. 1443-1451, May 2004.

  4. Optimum Buffer Size for Dynamic Voltage Processors
    A. Manzak and C. Chakrabarti
    Proc. of the 14th Int Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)}, Sep 2004.

  5. Packet Transmission Policies for Battery Operated Communication Systems
    Y. Li and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, Oct 2004

  6. Memory Subbanking Scheme for High Throughput Turbo Decoders
    M. Tiwari, Y. Zhu and C. Chakrabarti
    Proc. of Int. Conf on Acoustics, Speech and Signal Processing, May 2004.

  7. Parametrized SoC Design for Portable Systems
    S. Bhutoria and C. Chakrabarti
    Proc. of Int. Symp. on Circuits and Systems, May 2004.

  8. A Dynamic Task Scheduling Algorithm for Battery Powered DVS Systems
    A. Jameel and C. Chakrabarti
    Proc. of Int. Symp. on Circuits and Systems, May 2004.

  9. A Leakage Estimation and Reduction Technique for Scaled CMOS Logic Circuits Considering Gate Leakage
    H. Rahman and C. Chakrabarti
    Proc. of Int. Symp. on Circuits and Systems, May 2004.

2003

  1. A High Performance JPEG 2000 Architecture
    K. Andra, C. Chakrabarti and T. Acharya.
    IEEE Trans on Circuits and Systems for Video Technology, pp. 209-218, March 2003.

  2. Variable Voltage Task Scheduling Algorithms for Minimizing Energy/Power
    A. Manzak and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp. 270-276, April 2003.

  3. `Energy Efficient Turbo-based Space-Time Coder
    Y. Zhu, L. Li and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, 2003

  4. Battery-Friendly Design of Signal Processing Algorithms
    P. Raghavan and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, 2003

2002

  1. An Approach to Switching Activity Consideration during High Level Low Power Design Space Exploration
    R. Henning and C. Chakrabarti.
    IEEE Trans on Circuits and Systems II, pp. 339-351, May 2002.

  2. A VLSI Architecture for Lifting-Based Forward and Inverse Wavelet Transform
    K. Andra, C. Chakrabarti and T. Acharya.
    IEEE Trans on Signal Processing, pp. 966-977, April 2002.

  3. A Low Power Scheduling Scheme with Resources Operating at Multiple Voltages
    A. Manzak and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp 6-14, Feb 2002.

  4. Battery-aware Task Scheduling for a System-on-a-Chip Using Voltage/Clock Scaling
    P. Chowdhury and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, 2002

  5. Low Power Approach for Decoding Convolutional Codes with Adaptive Viterbi Algorithm Approximation
    R. Henning and C. Chakrabarti
    Proc. of International Symposium on Low Power Electronic Design, 2002.

  6. Battery-Conscious Task Sequencing for Portable Devices including Voltage/Clock Scaling
    D. Rakhmatov, S. Vrudhula and C. Chakrabarti
    Proc. of Design Automation Conference, 2002.

  7. Energy-Efficient Design of Turbo Decoders
    J. Kaza and C. Chakrabarti
    Proc. of International Conference on Acoustics, Speech and Signal Processing, 2002.

  8. Architectural Approaches to Reducing Leakage Energy in Caches
    S. Tadas and C. Chakrabarti
    Proc. of International Symposium on Circuits and Systems, 2002.

  9. A High Performance JPEG 2000 Architecture
    K. Andra, T. Acharya and C. Chakrabarti
    Proc. of International Symposium on Circuits and Systems, 2002.

2001

  1. Memory Design and Exploration for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti.
    Journal of VLSI Signal Processing, pp.167-178, Nov 2001.

  2. Data Memory Design and Exploration for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti.
    ACM Transactions on Design and Automation of Electronic Systems, pp. 553-569, Oct 2001.

  3. Voltage Scaling for Energy Minimization with QoS Constraints
    A. Manzak and C. Chakrabarti
    Proc. of International Conference on Computer Design, 2001.

  4. Variable Voltage Task Scheduling for Minimizing Energy
    A. Manzak and C. Chakrabarti
    Proc. of International Symposium on Low Power Electronic Design, 2001.

  5. Efficient VLSI Implementation of Bit Plane Coder of JPEG2000
    K. Andra, T. Acharya and C. Chakrabarti
    Proc. of SPIE Applications of Digital Image Processing, 2001

  6. Energy-Efficient Address Code Generation for Digital Signal Processors
    S. Udayanarayanan and C. Chakrabarti
    Proc. of Design Automation Conference, 2001

  7. An Approach for Enabling DCT/IDCT Energy Reduction Scalability in MPEG-2 Video Codecs
    R. Henning and C. Chakrabarti
    Proc. of International Conference on Acoustics, Speech and Signal Processing, 2001.

  8. An Efficient Implementation of a Set of Lifting Based Wavelet Filters
    K. Andra, C. Chakrabarti and T. Acharya
    Proc. of International Conference on Acoustics, Speech and Signal Processing, 2001.

2000

  1. VLSI Architectures for Weighted Order Statistic Filters
    C. Chakrabarti and L. Lucke.
    Signal Processing, vol.80, pp.1419-1433, 2000.

  2. Low Power Scheduling with Resources Operating at Multiple Voltages
    W.-T. Shiue and C. Chakrabarti.
    IEEE Transactions on Circuits and Systems II, June 2000.

  3. A Multibit BInary Arithmetic Coding Technique
    K. Andra, T. Acharya and C. Chakrabarti
    Proc. of International Conference on Image Processing, 2000.

  4. A VLSI Architecture for Lifting Based Wavelet Transform
    K. Andra, C. Chakrabarti and T. Acharya
    Proc. of IEEE Workshop on Signal Processing Systems, 2000.

  5. A Quality-Energy Tradeoff Approach for IDCT Computation in MPEG-2 Video Decoding
    R. Henning and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, 2000.

  6. Low Power Multi-module Multi-port Memory Design for Embedded Systems
    W.-T. Shiue, S. Tadas and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, 2000.

  7. Variable Voltage Task Scheduling for Minimizing Energy or Minimizing Power
    A. Manzak and C. Chakrabarti
    Proc. of International Conference on Acoustics, Speech and Signal Processing, 2000.

  8. Energy-efficient Code Generation for the DSP56000 family
    S. Udayanarayanan and C. Chakrabarti
    Proc. of International Symposium on Low Power Electronic Design, 2000.

  9. Relating Data Characteristics to Transition Activity in High-level Static CMOS Design
    R. Henning and C. Chakrabarti
    Proc. of VLSI Design 2000

  10. ILP-based Scheme for Low Power Scheduling with Resource Binding
    W.-T. Shiue and C. Chakrabarti
    Proc. of the International Symposium on Circuits and Systems, 2000.

  11. A Programmable Processor for Cryptography
    S. Raghuram and C. Chakrabarti
    Proc. of the International Symposium on Circuits and Systems, 2000.

1999

  1. Efficient realizations of encoders and decoders based on the 2-D Discrete Wavelet Transform
    C. Chakrabarti and C. Mumford.
    IEEE Transactions on VLSI Systems, pp. 289-298, Sep 1999.

  2. A new register allocation scheme for data format converters
    K. Srivatsan, C. Chakrabarti and L. Lucke.
    IEEE Transactions on Circuits and Systems II, pp. 1250-1253, Sep 1999.

  3. Memory Exploration for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti
    Proc. of the Design Automation Conference, 1999

  4. Instruction-level power model of microcontrollers
    C. Chakrabarti and D. Gaitonde
    Proc. of the International Symposium on Circuits and Systems, 1999

  5. A low power scheduling scheme with resources operating at multiple voltages
    A. Manzak and C. Chakrabarti
    Proc. of the International Symposium on Circuits and Systems, 1999

  6. Memory Design and Exploration for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti
    Proc. of the Design and Implementation of Signal Processing Systems, 1999

  7. A DWT based encoder architecture for symmetrically extended images
    C. Chakrabarti
    Proc. of the International Symposium on Circuits and Systems, 1999

  8. Activity Models for use in Low Power, High Level Synthesis
    R. Henning and C. Chakrabarti
    Proc. of the International Conference on Acoustics, Speech and Signal Processing, 1999

1998

  1. Hardware Design of a 2-D Motion Estimation System based on the Hough Transform
    H. Li and C. Chakrabarti.
    IEEE Transactions on Circuits and Systems II, vol. 45, no. 1, pp. 80-95, Jan 98.

  2. Low Power Scheduling with Resources Operating at Multiple Voltages
    W.-T. Shiue and C. Chakrabarti
    Proc. of the International Symposium on Circuits and Systems, 1998

  3. VLSI Architectures for Weighted Order Statistic Filters
    C. Chakrabarti and L. E. Lucke
    Proc. of the International Symposium on Circuits and Systems, 1998

1997

  1. High-Level design Synthesis of a Low Power VLIW Processor for the IS-54 VSELP Speech Encoder
    R. Henning and C. Chakrabarti
    Proc. of the International Conference on Computer Design, 1997

1996

  1. A survey of VLSI architectures for Wavelet Transforms
    C. Chakrabarti, M. Vishwanath and R. M. Owens.
    Journal of VLSI Signal Processing}, vol. 14, no. 2, pp. 171-192, Nov 1996.

  2. Motion Estimation of 2-Dimensional Objects Based on the Straight Line Hough Transform: A New Approach
    H. Li and C. Chakrabarti.
    Pattern Recognition, vol. 29, no. 8, pp. 1245-1258, Aug 1996.

  3. A New Architecture for the Viterbi Decoder for Code Rate k/n
    H. Li and C. Chakrabarti.
    IEEE Trans on Communications, pp. 158-164, Feb 1996.

  4. Scheduling for Minimizing the Number of Memory Accesses in Low Power Applications
    R. Saied and C. Chakrabarti
    Proc. of the VLSI Signal Processing Workshop, 1996

  5. Hardware Implementation of a 2-D Motion Estimation System Based on the Hough Transform
    H. Li and C. Chakrabarti
    Proc. of the International Symposium on Circuits and Systems, 1996

  6. Efficient Realizations of Analysis and Synthesis Filters based on the 2-D Discrete Wavelet Transform
    C. Chakrabarti and C. Mumford
    Proc. of the International Conference on Acoustics, Speech, and Signal Processing, 1996

1995

  1. Architectures for Hierarchical and Other Block Matching Algorithms
    G. Gupta and C. Chakrabarti.
    IEEE Transactions on Circuits and Systems for Video Technology, pp. 477-489, Dec 1995.

  2. Efficient Realizations of the Discrete and Continuous Wavelet Transforms: from single chip implementations to mappings on SIMD array computers
    C. Chakrabarti and M. Vishwanath.
    IEEE Trans on Signal Processing, pp.759-771, March 1995.

  3. A Digit-Serial Architecture for Gray-Scale Morphological Filtering
    L. E. Lucke and C. Chakrabarti
    IEEE Trans on Image Processing, pp. 387-391, March 95.

  4. Low Power Data Format Converter Design using Sem-Static Register Allocation
    K. Srivatsan, C. Chakrabarti and L. Lucke.
    Proc. of the International Conference on Computer Design, 1995

  5. A Parallel Programmable Architecture for Linear and Nonlinear Filters
    L. Lucke and C. Chakrabarti.
    1995 IEEE Workshop on on Nonlinear Signal and Image Processing, pp. 891-894, 1995.

  6. A New Viterbi Decoder Design for Code Rate k/n
    H. Li and C. Chakrabarti.
    Proc. of the IEEE International Conference on Acoustics, Speech, and Signal Processing, 1995.

  7. Architectures for the Discrete and Continuous Wavelet Transforms
    C. Chakrabarti, M. Vishwanath and R. M. Owens.
    Proc. of the IEEE International Conference on Acoustics, Speech, and Signal Processing, 1995.

  8. Efficient Architectures for Hidden Surface Removal
    C. Chakrabarti and L. Lucke.
    Proc. of the First IEEE International Conference on Image Processing, 1995.

1994

  1. Novel Sorting Network-Based Architectures for Rank-Order Filters
    C. Chakrabarti and L. Y. Wang.
    IEEE Transactions on VLSI Systems, pp. 502-507, Dec 1994.

  2. High Sample Rate Architectures for Median Filters.
    C. Chakrabarti.
    IEEE Trans on Signal Processing, vol. 42, no. 3, pp. 707-712, March 1994.

  3. A Digit-Serial Architecture for Gray-Scale Morphological Filtering
    L. E. Lucke and C. Chakrabarti
    IEEE International Symposium on Circuits and Systems, vol. 4, pp. 207-210, 1994.

  4. Novel Sorting Network-Based Architectures for Rank-Order Filters
    C. Chakrabarti and L. Y. Wang.
    IEEE International Symposium on Circuits and Systems, vol. 3, pp. 89-92, 1994.

  5. High Sample Rate Architectures for Block Adaptive Filters.
    S. Karkada, C. Chakrabarti and A. Spanias.
    IEEE International Symposium on Circuits and Systems, vol. 4, pp. 131-134, 1994.

  6. VLSI Architectures for Hierarchical Block Matching
    G. Gupta and C. Chakrabarti.
    IEEE International Symposium on Circuits and Systems, vol. 4, pp. 215-219, 1994

  7. A VLSI Architecture for Real-Time Hierarchical Encoding/Decoding of Video using the Wavelet Transform
    M. Vishwanath and C. Chakrabarti.
    IEEE International Conference on Acoustics, Speech, and Signal Processing, 1994.

1993

  1. Sorting Network based Architectures for Median Filters
    C. Chakrabarti.
    IEEE Trans on Circuits and Systems}, vol. 40, no. 11, pp.723-727, Nov 1993.


Chaitali Chakrabarti
Professor
chaitali@asu.edu