ASU EEE425/591A(NTU 740-W) COURSE OUTLINE

DIGITAL INTEGRATED CIRCUITS AND SYSTEMS

CLASS MEETS ON CAMPUS in SCOB 105(8:30-9:45 A.M.):  75 minute sessions Mon thru Thurs
SCHEDULE LNs:  EEE425;40845  and  EEE591A;49335
PREREQUISITES: COURSE(S) IN ELECTRONIC CIRCUITS AND DIGITAL LOGIC
TEXTBOOK:  "DIGITAL INTEGRATED CIRCUITS" by DEMASSA, CICCONE, John  Wiley & Sons,'96

INSTRUCTOR; Thomas A. DeMassa, Professor Emeritus
                             DeMassa@asu.edu
                             http://www.public.asu.edu/~demassa
                             Office hrs: ERC513, 10 to --  AM

 EE 425 Lab Schedule

2 EXAMS and the FINAL will be in ROOM PS H 135; 8:30 to 9:45. The dates are 6/17(MON), 7/8(MON) and 7/18(TH)

COURSE DESCIPTION: DIGITAL INTEGRATED CIRCUITS WITH EMPHASIS ON CMOS. OPERATION AND DESIGN OF TTL, ECL, NMOS, CMOS AND GaAs DIGITAL LOGIC CIRCUITS. ADDITIONAL TOPICS INCLUDE BiCMOS AND SEMICONDUCTOR MEMORY CIRCUITS.
COURSE OBJECTIVES: TO PROVIDE EXTENSIVE KNOWLEDGE OF THE OPERATION AND DESIGN OF DIGITAL ICs INCLUDING TTL, ECL, NMOS, AND CMOS TECHNOLOGIES WITH EMPHASIS ON CMOS; TO INTRODUCE BiCMOS AND TO PROVIDE AN EXTENSIVE DESCRIPTION OF THE OPERATION AND DESIGN OF GaAs DIGITAL LOGIC FAMILIES; TO PROVIDE COMPUTATIONAL AND SPICE COMPARISONS REGARDING THE VOLTAGE TRANSFER CHARACTERISTIC, FAN-OUT, POWER DISSIPATION AND SPEED OF EACH; TO PROVIDE A DES-CRIPTION OF RANDOM ACCESS MEMORY (RAM) AND READ-ONLY MEMORY(ROM).
TV COURSE: Since the circuits are difficult to see on the TV screen,  bring your text to class daily.

HOMEWORK:  Assigned daily and collected on Exam 1, Exam 2 and Final Exam days

EXAMINATIONS: 2 MID-TERMS AND A FINAL EXAM (All Open Book & Closed Notes) GRADING:  2 EXAMS ,60%;  FINAL EXAM,30%;  HW,10%(all exams 1hr & 15m)                       OR  2 EXAMS,50%;  FINAL EXAM,20%;  LAB,20%;  HW,10%

 
COURSE GRADES
 

COURSE OUTLINE BY TOPICAL AREAS AND CHAPTERS

LECTURE 1(TUES 5/28) HOMEWORK PROBLEMS ASSIGNED(HPA): 1.1,4,22,25

PROPERTIES OF DIGITAL CIRCUITS: inverting and noninverting gates, ideal logic elements, voltage transfer characteristic(VTC), logic swing, transition width, noise, fan-in, fan-out, transient characteristics,rise and fall times, power dissipation, power-delay product
LECTURE 2 (WED 5/29) HPA: 16.6,8;  17.12,19 LECTURE 3 (THUR 5/30)  HPA:  18.1,2,10;  19.1,2,17 LECTURE 4 (MON 6/3) HPA:  20.1,2,17;  21.1,2,11
ENHANCEMENT-DEPLETION LOADED NMOS INVERTER: operation, graphical determinationof VTC, calculation of critical voltages, power dissipation, SPICE simulation
LECTURE 5 (TUES 6/4) HPA: 22.2,5,9,31,38,40,43 LECTURE 6 & 7 (WEDS 6/5, THUR 6/6) HPA:  23.1,2,14,25,26,32 LECTURE 8(MON 6/10) HPA: 24.1,2,3,4,7,12,13,21,31,34 LECTURE 9 & 10 (TUES, 6/11, WEDS 6/12)HPA: 25.1,3,7,11; 26.1,3,8,10,13;  27.1,5,7;  28.2,4,8,16,19
CMOS TRI-STATE LOGIC GATES: high impedance Z-states, contention X-states, tri-state inverters, applications, transmission gates  CMOS SCHMITT TRIGGER GATES: inverter, operation and VTC, design, buffered, output, feedback, NAND gate. CMOS DRIVERS: cascaded inverters driving a load cap, multi-stage inverter driver. DYNAMIC CMOS
LECTURE 11 (THURS 6/13) MID-TERM EXAM 1 REVIEW
MID-TERM EXAM  1 (MON  6/17, ROOM PS H 135)

 
 
 

LECTURE 12 (TUES, 6/18 )HPA: 2.1,2; 3.6,14; 4.1,8,22

DIODES: PN junction and MN Schottky, modeling, capacitance, SPICE model, diode uses(diode-resistor logic, level-shifting and clamping diodes). BIPOLAR JUNCTION TRANSISTORS (BJTs): junction isolated and oxide isolated NPNs, multi-emitter,Schottky-clamped, lateral PNP, Ebers-Moll model,  BJT modes of operation, SPICE model, IC resistors and diodes. INTRODUCTION TO BJT DIGITAL CIRCUITS: analysis, BJT inverter, power dissipation,
LECTURE 13&14 (WEDS 6/19; THUR 6/20)  HPA:  5.1,6,22;6.1,3,7,10; 7.1,11,18;  8.1,3,6,8,9;  9.1,5,13
SCHOTTKY TRANSISTOR-TRANSISTOR LOGIC (STTL): Schottky diodes, Schottky BJTs, STTL inverter, NAND gate, VTC, fan-out, powerdissipation, NAND GATE,low power LSTTL, SPICE simulation.
 

REVIEW & RETURN MID-TERM EXAM 1 (MON 6/24)
 

LECTURE 15(TUES 6/25)HPA: 10.3,4 LECTURE 16( WEDS 6/26)HPA: 11.1,6,8,13,19;  12.1,4,7,10 LECTURE 17(THURS 6/27 MON 7/1)HPA:  13.1,3,10,14; 14.1,5,8,10 LECTURE 18(TUES 7/2) TTL and ECL Review and Problem session
see special problems in Chapters 7 through 14(some answers 7.1,7.2,7.4; 8.2,8.3;9.1, 9.2, 9.3;  10.1, 10.2,10.3;  11.1, 11.3,11.4; 12.1,12.2,12.3; 13.1, 13.2, 13.3; 14.1, 14.2, 14.3)

LECTURE 19(WEDS 7/3) HPA: 34.3,6,7,10

GaAs METAL SEMICONDUCTOR FETs (MESFETs): MESFET fabrication, MESFET IV Characteristics, N-channel, E-D, E-O, modes of operation, transconductance parameter, threshold voltage, capacitance, SPICE simulation
 
 

 THURSDAY  JULY 4
INDEPENDENCE DAY HOLIDAY
 
 
MID-TERM EXAM  2 (MON  7/8, ROOM PS H 135)
(Chapters 1 thru 14)
 
 

LECTURE 20  (TUES 7/9) HPA: 35.2,5,7,10

DIRECT COUPLED NMESFET INVERTER (DCFL): E-O inverter, operation, graphical determination of VTC, calculation of critical voltages, power dissipation, fan-out, SPICE simulation
LECTURE 21 (WEDS 7/10) HPA: 36.2,3,4,6;  37.1,2,3,4
SCHOTTKY DIODE NMESFET LOGIC (SDFL) INVERTER: E-D inverters,operation, calculation of critical voltages, power dissipation, fan-out, SPICE simulation.
BUFFERED NMESFET LOGIC (BFL) INVERTER: same as SDFL inverter.
LECTURE 22 (Thurs 7/11) HPA:  39.1,2,3,9
Review DCFL, SDFL , BFL and SCFL GaAs digital ICs. GaAs LOGIC FAMILY GATES: DCFL NOR, NAND and OR GATES, SDFL NOR and NAND gates, BFL NOR and NAND gates, complex AOI & OIA gates, DCFL XOR, other OR/NOR gates and GaAs Digital IC Problem Session
REVIEW & RETURN MID-TERM EXAM 2 (MON,7/15)
 
 

LECTURE 23( TUES 7/16)   ROMs and RAMs Ch 31 and 32 and BJT Digital IC Review for Final Exam

LECTURE 24(Weds 7/17) Review NMOS and CMOS and CMOS Problem Session(See problems in Chapters 16 thru 25;some answers:  23.1,  2,  3, 4 and 5;   24. 2,    4,    6,   8,   10; 25.1, 2,   3,   4,   5, 6

          FINAL EXAM  (Thursday 7/18, ROOM PS H 135)
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CURRENT LAB GRADES

One Day Short Course:  1.Introduction, Fundamentals, Diodes and BJTs; 2.BJT DICs; 3.NMOS and NMOS DICs; 4.CMOS and CMOS DICs; 5.BiCMOS DICs and GaAs DICs

Two Day Short Course:

Session 1(Introduction, Fundamentals),
Session 2(Diodes and BJTs and BJT DICs),
Session 3 & 4(Schottky BJTs,STTL,ECL),
 
Session 5(Advanced ECL),
Session 6,(NMOS and NMOS DICs)
Session 7 & 8(CMOS and CMOS DICs),
Session 9 & 10(BiCMOS DICs and GaAs DICs and recap)
 

White EXAM 1 SOLUTIONS(Su01)

Blue EXAM 1 SOLUTIONS(Su01)

White EXAM 2 SOLUTIONS(Su01)

Blue EXAM 2 SOLUTIONS(Su01)
 
 
 

 The following EXAM is an Example of Exam3. ENJOY
1,1B,  2,   3,  4,4B, 5,  Special
 
 
 
Su 02 Course Outline

 Fa 00 Course Outline

Homework Solutions(Exam1)

Homework Solutions(Exam2)
 


PSPICE Helper

EE 425 Lab Schedule

Lab Manual

Lab Write-up

Book Corrections

Book Corrections(1st printing)

CHECK OUT THESE Simulations

DTL-STTL SPICE SIMULATIONS:Ch 7, Ch 8, Ch 9, Ch 10

ECL SPICE SIMULATIONS:  Ch11-15,
 
 
 
 

Fa 2000 SPICE Assignments  due dates TBA

SPICE SIMULATION Assignment 1: Simulate two of the circuits in each of the Chapters 8,9,10,11,12 and 15.

SPICE SIMULATION Assignment 2: Simulate two of the circuits in each of the EVEN Chapters 16 - 30
 

CHECK THESE SIMULATIONS OUT
NMOS SPICE SIMULATIONS:  Ch16-22aCh16-22b
CMOS SPICE SIMULATIONS: Ch23-25, Ch26
GaAs SPICE SIMULATIONS: Ch35-38
ROM SPICE SIMULATIONS: Ch32

Homework Answers:

See text; pages 674-678 

Exam Solutions:

Will be discussed ASAP. 

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