Several FinFET devices shown below with varying fin width have been simulated. Gate lengths of 10 nm and oxide thickness of 1.75 nm have been used in all the simulations. The fin is assumed to be lightly doped with a thickness varying from 6 nm to 12 nm. 

Left panel – 3D schematic view. Right panel – top view along A-A’ cross section.

For the 12 nm fin width our simulation shows the formation of a distinct channel on each side of the fin (see the figure below). As fin width decreases gradually from 12 nm towards 8 nm, inversion layer formed adjacent to both gates merge into a single channel as shown in the figure (middle and right panel).

Channel formation: Electron density along A-A’ cross section. Left panel: fin width=12nm, middle panel: fin width=10nm, right panel: fin width=8nm.

The transfer characteristics for different fin widths are shown below. The data for 12nm fin width near subthreshold regime is in good correspondence to the experimental data. We found that the effect of the fin width variation is more important for the subthreshold device behavior than for higher gate voltages (the linear scale is not shown here).

Transfer characteristics V_d=0.1 V: left panel - comparison with the experiment; right panel - the same for different fin widths.

The device turn-off behavior has been examined by extracting sub-threshold slope for different fin widths. The corresponding data are shown below:

Subthreshold slope vs. fin width.

It has been found that as the fin width decreases, the gate control improves linearly up to the fin width of 8 nm and then saturates with the further decreasing of the fin width. For 12 nm fin width the calculated value of the subthreshold slope is 126 mV/dec, as compared to 125mV/dec experimental value.

These results were presented at IWCE-11 (http://www.iwce.org)