In order to answer this question we have optimized 10 nm gate length FinFET to meet ITRS requirements for double-gate high performance (HP) logic technology devices, which are expected to be commercially available in year 2015. After a series of extensive simulations it has been found that the device on-current approaching the value projected by ITRS can be obtained using conventional Si channel and SiO₂ gate insulator. The simulation results show that quantum mechanical effects significantly enhance the intrinsic switching speed of the device. The theoretical value of intrinsic switching speed for the considered device exceeds the ITRS projected values. The full set of performance matrices for the optimized FinFET is given in the table below:

[3] International Technology Roadmap for Semiconductors (ITRS), 2006-update Edition, http://public.itrs.net 

We have investigated the impacts of fin width, gate-source/drain underlap regions and doping profiles to define critical issues regarding performance optimization (Fig. 1 and 2). In addition to the enhancement in on-current values due to the quasi-ballistic nature of the transport, it has been found that the intrinsic switching speed is greatly improved due to the quantum confinement effects, which are also important in the gates. This important effect is often ignored in numerical simulations due to over-simplified gate treatment.

            

Fig. 1. On-current and sub-threshold source-to-drain leakage current as a function of fin width tSi for the considered FinFET.

Fig. 2. Values of on-current, subthreshold source-to-drain leakage and gate leakage as functions of doping gradient gdop.

We find that while the effect of poly-Si gate depletion is predictably very small in highly-doped gates, the quantum-mechanical confinement starts to play an important role in the gates, effectively in-creasing the electrical equivalent oxide thickness (EOTelec), which, in turn, decreases the device capacitance and improves the intrinsic switching speed. This phenomenon can be illustrated by the distribution of the change in charge shown in Figure 3 (for large step gate voltage) and in Figure 4 (for small signal applied at gates):

            

Fig. 3. 2D distribution of the large-signal change in density ("capacitive" charge).           Fig. 4. 2D distribution of the small-signal change in density ("capacitive" charge).

Summary

We has found that for the considered optimized FinFET, it is theoretically possible to achieve the intrinsic switching speed up to 9 THz for digital applications, and cut-off frequency up to 3 THz for analog applications. Importantly, our simulation indicates that this performance can be achieved using the conventional non-strained Si channel and a rather realistic (2 nm/dec) doping profile. Our simulations clearly demonstrate that with a proper choice of geometry and doping, Si FinFETs will fulfill ITRS specifications for 10 nm HP devices.

These results will be presented at IWCE-12 (http://www.iwce.org)