Ke Bai 
Ph. D Candidate /
Research & Teaching Associate
Arizona State University
I was born in Chongqing, China and lived there until I got into University of Science and Technology of China, where I received B. S. in Electrical Engineering in 2008 (a.k.a F04). Now, I am a Ph. D. in Computer Science at Arizona State University. I am a member of Compiler Microarchitecture Lab (CML) supervised by Prof. Aviral Shrivastava.
Take a look at my Resume in PDF format.
Research
Interests
I am interested in all interesting Computer Science problems, especially in compiler construction, high performance computing, multi-core optimization and programming. My goal is making multi-core and multi-thread programming easier. My list of interesting topics:
- Design
of cutting edge software for multi-core processors and clusters;
- Design
of programming model for multi-core processors;
- Computer
architecture and compilers design and optimization for multi-core and
graphics processors;
- Interaction
of software and hardware;
- Performance
evaluation and management on power-efficient
systems.
For more information of my research,
please email me: Ke Dot Bai At
asu Dot edu
Publications
Conference Papers
1.
Ke
Bai, Di Lu and Aviral Shrivastava, "Vector Class on Limited Local Memory
(LLM) Multi-core Processors", In Proceedings of the International
Conference on Compilers Architectures and Synthesis of Embedded Systems (CASES), 2011.
2.
Ke
Bai, Aviral Shrivastava and Saleel Kudchadker, "Stack Data Management for Limited Local
Memory (LLM) Multi-core Processors", In Proceedings of the
International Conference on Application-specific Systems, Architectures and
Processors (ASAP), 2011.
3.
Ke
Bai and Aviral Shrivastava, "Heap Data Management for Limited Local Memory
(LLM) Multi-core Processors" In Proceedings
of the International Conference on
Hardware/Software Codesign and System Synthesis (CODES+ISSS),
2010.
4.
Seung
chul Jung, Aviral Shrivastava, and Ke Bai, "Dynamic Code Mapping for Limited Local
Memory Systems ", In Proceedings of
the International Conference on Application-specific Systems, Architectures and
Processors (ASAP), 2010.
Journal Articles
1.
Ke Bai and Aviral
Shrivastava, "A Software-Only Scheme for Managing
Heap Data on Limited Local Memory (LLM) Multi-core Processors", [To be
Published] in ACM Transactions in
Embedded Computing Systems (TECS).
2.
Ke Bai, Seungchul Jung, and Aviral Shrivastava, "Efficient Code Placement Techniques for
Limited Local Memory Multi-core Processors", [submitted to] ACM
Transactions on Design Automation of Electronic Systems (TODAES)
3.
Ke Bai and Aviral Shrivastava, "A Pure
Software Technique for Stack Data on Limited Local Memory Multi-core
Processors", [submitted to] IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems
(TCAD)
Projects
Limited Local Memory Multicore
Project
My project page is moved to my lab website. Content includes:
- Introduction
- Challenge
- A paradigm shift in
computing
- Limited Local Memory (LLM)
Architectures
- Thread Memory
Management
- Overview of our Approach
- LLM Memory Manager [Download]
Some In-Class Projects
1. Design and implementation
of a mini object Pascal compiler
- Front
End: Implemented a translation scheme to check input programs written
with an objected-oriented language derived from Pascal for semantic
errors by utilizing scanner and parse generator tools (lex and yacc).
- Middle End: Generated three-address
code and implemented some basic optimizations on the code including
evaluation of constant expressions, elimination of redundant expressions
using value numbering, and global redundancy elimination.
- Back End: Implemented a C backend
that transforms three-address code into C programs in a form with support
for global, heap variables, methods and arrays.
2. Implementation of software on high
performance cluster (ASU saguaro 5000 processors)
- OpenMP: Accelerated the performance of
"Poisson Equation Solver" using OpenMP
with particular attention to data dependencies.
- MPI and hybrid MPI-OpenMP: Implemented the "2-phase simplex
method" for a parallel distributed system with MPI and hybrid MPI-OpenMP.
- CUDA: Implemented an image
manipulation filter called "emboss" on GPU.
- MPI: Set up a Singular Value
Decomposition on the input image using BLACS and ScaLAPACK
(A = U* S*V), created a new matrix S2 where S is shrinked
by half in each direction, and outputted A2 = U2*S2*V2 as binary using
MPI-IO to a BMP file.
3. Implementation
of multi-core/multi-threaded programs on the IBM Cell Broadband Engine
- Developed
an "N-body simulator" which distributes its computing task and
data to SPEs.
- Optimized the software using SIMD
hardware characteristic and double buffering software technique.
- Evaluated performance improvement
with Systemsim
simulator.
4. Implementation
of a scalable video coding/decoding framework for real-time dynamic channel
band-width under multi-user scenario, using JSVM (Joint Scalable Video Model)
software framework.
5. Implementation
of a Scull Char driver, a parallel port, an interrupt driven parallel port for
Linux kernel 2.4.
Honors and
Awards
- Research Assistantship, Arizona
State University, August 2008 – present
- University Graduate Grant, Arizona
State University, 2008
- GPSA Travel Awards, Arizona State
University, 2010/2011
- Scholarship for Excellent Students,
University of Science and Technology of China, 2005 – 2008
- The bronze medal at Robert Game,
University of Science and Technology of China, 2006
- Excellent leader, University of
Science and Technology of China, 2006/2007