Reiley Jeyapaul

I am a Research Associate at the Compiler Microarchitecture Lab in the School of Computing, Informatics, and Decision Systems Enegineering(ASU). My doctoral research focus is in developing compiler and compiler-based solutions, to improve system reliability and reduce power consumption, in today's and future computing systems.

Take a look at my Resume in PDF format or MS Word format

Upadates!

• [Oct 2011] In the News! An article on my research at CML, was featured in ACM Technews. Original article by Joe Kullman (ASU News).
• [Oct 2011] Presented my paper on Smart Cache Cleaning at CASES'11-International Conference on Compilers, Architectures and Synthesis of Embedded Systems, at Taipei, Taiwan.
• [Sep 2011] Presented my papers on UnSync and CGRA Multithreading, at ICPP'11-International Conference on Parallel Processing, at Taipei, Taiwan.
• [Apr 2011] Succesfully completed PhD Candidacy Examination.

Research Interests

• Compiler optimizations
• Design and Analysis of Processor Microarchitectures (Embedded, Single-core and Multi-core)
• Fault Tolerance techniques for High Performance Computing systems.
• Analytical and Computational modeling of the processor.
• Fault injection testing of chips (at the RTL) for soft error failure rate estimation.

Brief History

B.E.(2000 ~ 2004) from Univ of Madras, India.

Software Engineer (2004 ~ 2006) Larsen & Toubro Infotech Ltd, Chennai, India.

M.S.(2006 ~ 2008) in Electrical Engineering at Arizona State University.

Ph.D(January 2009 ~ till date) in Computer Science at Arizona State University.