About Reiley
Reiley graduated from the University of Madras, India with a B.E (Electronics and Communication Engineergin) in 2004. He then joined Larsen & Toubro Infotech, Ltd., India, as a Software Engineer. He received his MS (Electrical Engineering) degree from Arizona State University in 2008. He has been associated with Prof. Aviral Shrivastava at the Compiler Microarchitecture Lab, SCIDSE, ASU, as a Research Associate since Aug 2006, where he continued on to pursue doctoral research.
His research focus is in developing compiler-based solutions to improve system reliability through analytical modeling and analysis of the processor microarchitecture. His other areas of interest include: (1)developing compiler solutions to enable the efficient use of CGRAs and such power-efficient many:w -core architectures; and (2)developing hybrid compiler-microarchitecture solutions to reduce embedded system power consumption.
He is currently, a Candidate for a Doctoral degree in Computer Science, from the School of Computing, Informatics and Decision Systems Engineering. He is in the final stages of his doctoral expedition, and plans to be hooded in May 2012.
