Projects involved in as part of...
Research at CML (2006 ~ till date)
- CE3S: Compiler Enhanced Energy Efficient Shielding of Registers
- Code Transformation Technique to reduce TLB switching energy
- Compiler Technique to Mitigate Failures due to Soft Errors
MS coursework at ASU (2006 ~ 2008)
- Design of Out-Of-Order Issue Queue for 4-issue processor
- Design and Development of 4KB SRAM memory bank
- Low-Power Design of a Multi-Bit Viterbi Decoder
BE coursework at Univ of Madras (2000 ~ 2004)
Research at CML (2006 ~ till date)
CE3S: Compiler Enhanced Energy Efficient Shielding of Registers
Through analysis and experiments, determined that the register usage pattern can be altered by the compiler and therefore a fixed order of registers can be shielded. Using a fixed register-order for shielding with highly vulnerability data would greatly reduce the energy overhead and also vulnerability reduction of Register File. Designed and implemented a compiler register reallocation algorithm to ensure highly-vulnerable and least accessed variables to specific order of registers. The algorithm was implemented in the GCC (v2.6.3) compiler.
Code Transformation Technique to reduce TLB switching energy
Developed a novel access-reordering code transformation technique to reduce the number of page switches in the TLB. Implemented the technique for a new TLB architecture (use-last) designed by Intel. Experimentally demonstrated the reduction in energy dissipation of processors.
Compiler Technique to mitigate failures due to Soft Errors
Developed a compiler technique to alter the data access pattern in a program, thereby reducing the failure rate (due to soft errors), of the system. Analyzed various code transformations to determine their impact on vulnerability. Implemented an analytical cache model for failure rate estimation. Experimentally demonstrated the impact of the transformations using SimpleScalar cycle-accurate simulator.
MS coursework at ASU (2006 ~ 2008)
Design of Out-Of-Order Issue Queue for 4-issue processor
Designed an energy efficient and fast issue queue using CAM arrays to store data. A priority encoding logic was implemented for oldest-first execution of instructions. The issue queue consisted of 32 entries and optimized for energy and performance.
Design and Development of 4KB SRAM memory bank
Designed a reliable 6T-SRAM memory bank to work across process corners. Designed all associated circuitry involved in the working of the memory bank. Schematic design and standard-cell layout practice for the memory bank.
Low-Power Design of a Multi-Bit Viterbi Decoder
Designed a fast and very low power multi-bit Viterbi Decoder. Schematic design and simulation using CADENCE-spectre design tools. Optimal Standard-Cell layout was practiced to realize the circuit in minimal area.
BE coursework at Univ of Madras (2000 ~ 2004)
Design and development of Microcontroller based Digital I/O Network Node
Real time system architecture and Programming of the microcontroller using Cross-C. Circuit design and design implementation using CADSTAR. Testing of the circuit using Bread-board testing and then integrated board testing.
