Conference Papers
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B2P2: Bounds Based Procedure Placement for Instruction TLB Power Reduction in Embedded Systems
NEW Reiley Jeyapaul and Aviral Shrivastava SCOPES 2010 :Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems |
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Cache Vulnerability Equations for Protecting Data in Embedded Processor Caches from Soft Errors
NEW Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul LCTES 2010 :Proceedings of the 2010 ACM SIGPLAN/SIGBED Conference on Language, Compilers and Tool support for Embedded Systems |
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Code Transformations for TLB Power Reduction Reiley Jeyapaul, Sandeep Marathe, and Aviral Shrivastava VLSI 2009 :Proceedings of the 22nd International Conference on VLSI Design |
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SPKM : A Novel Graph Drawing based Algorithm for Application Mapping onto Coarse-Grained Reconfigurable Architecture Jonghee Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, and Yunheung Paek ASPDAC 2008 :: Proceedings of the Asia and South Pacific Design Automation Conference |
Journal Articles
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Code Transformations for TLB Power Reduction
Reiley Jeyapaul, and Aviral Shrivastava IJPP :International Journal of Parallel Programming |
M.S. Thesis
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Reiley Jeyapaul Static Analysis to Mitigate Soft Error Failures in Processors Advisors: Aviral Shrivastava (Co-Chair), Lawrence T. Clark (Co-Chair), Yu (Kevin) Cao. |
