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660 S Mill Ave
Tempe, AZ 85281

yooseong dot kim at asu dot edu

I defended my thesis in January 2017 and graduated with the honorable `Computer Science Graduating PhD Student of the Year' award from School of Computing, Informatics, Decision Systems Engieering. Now I am a Senior R&D Engineer at Synopsys Inc., working on physical optimization of gate-level netlists in the next version of Design Compiler. See my LinkedIn page and Google Scholar page.


My research interests might be briefly termed 'architecture-aware compiler optimization'. I am generally interested in performance of programs on an architecture where programmability is limited. As processor design paradigm shifts to multi-cores, the complexity of hardware is continuously being moved to software. Programmers are facing a great deal of challenges of dealing with a lot of architecture-specific details that are crucial to performance (and sometimes even functionality), on top of writing parallel programs. A smart compiler can not only relieve the burden of programmers, but also do various optimizations tailored specifically to each individual application.

Especially, I am interested in the following topics:

Advisor: Prof. Aviral Shrivastava

Brief History

Intern (May 2016 - Aug. 2016) Intel, Hillsboro, OR
Visting Student Researcher (Jul. 2012 - Oct. 2014) EECS, University of California, Berkeley, Berkeley, CA
Summer Research Co-op (May 2014 - Aug. 2014) Powertrain Control Model-Based Design, Toyota Technical Center, Ann Arbor, MI
Ph.D. (Aug. 2009 - present) Computer Science, Arizona State University, Tempe, AZ
M.S. (Mar. 2007 - Feb. 2009) Computer Science and Engineering, Sogang University, Seoul, South Korea
Software developer (Feb. 2002 - Jun. 2004) FinalData Inc., Seoul, South Korea
B.E. (Mar. 2000 - Aug. 2006) Computer Science and Engineering, Sogang University, Seoul, South Korea

Publications and Peer-reviewed Poster Presentations

  • Yooseong Kim, David Broman, and Aviral Shrivastava, "WCET-Aware Function-level Dynamic Code Management on Scratchpad Memory", in ACM Transactions on Embedded Computing Systems, May 2017
  • Jian Cai, Yooseong Kim, Youngbin Kim, Aviral Shrivastava, and Kyoungwoo Lee, "Reducing Code Management Overhead in Software-Managed Multicores", in Proceedings of DATE, Lausanne, Switzerland, Mar. 2017
  • Youngbin Kim, Jian Cai, Yooseong Kim, Kyoungwoo Lee, and Aviral Shrivastava, "Splitting Functions in Code Management on Scratchpad Memories", in Proceedings of ICCAD (acceptance rate: 97/408=24%), Austin, Nov. 2016
  • Yooseong Kim, "Correct-by-Construction Timing of Cyber-Physical Systems Using Scratchpad Memories", in SIGDA PhD Forum at DAC, May 2016
  • Yooseong Kim and Aviral Shrivastava, "A Comparison of WCET-Centric Dynamic Management Techniques for Instruction Scratchpads", (submitted)
  • Yooseong Kim, David Broman, and Aviral Shrivastava, "Reducing WCET Using Function Splitting for Code Management on Software-Managed Multicores", in Work-in-Progress at DAC, Jun. 2015
  • Yooseong Kim, David Broman, Jian Cai, and Aviral Shrivastava, "WCET-Aware Dynamic Code Management on Scratchpads for Software-Managed Multicores", in Proceedings of RTAS (acceptance rate: 27/133=20%), Berlin, Germany, Apr. 2014
  • Yooseong Kim and Aviral Shrivastava, "Memory Performance Estimation of CUDA Programs", in ACM Transactions on Embedded Computing Systems, Sep. 2013
  • David Broman, Michael Zimmer, Yooseong Kim, Hokeun Kim, Jian Cai, Aviral Shrivastava, Stephen A. Edwards, and Edward A. Lee, "Precision Timed Infrastructure: Design Challenges", in Proceedings of ESLsyn, Austin, Jun. 2013
  • Jing Lu, Yooseong Kim, Aviral Shrivastava, and Chuan Huang, "Branch Penalty Reduction on IBM Cell SPUs via Software Branch Hinting", in Proceedings of CODES+ISSS (acceptance rate: 33/117=28%), pp.355-364, Taipei, Taiwan, Aug. 2011
  • Yooseong Kim and Aviral Shrivastava, "CuMAPz: A Tool to Analyze Memory Access Patterns in CUDA", in Proceedings of DAC (acceptance rate: 156/690=23%), pp.128-133, San Diego, Jun. 2011
Previous Publications
  • Yooseong Kim, Sangwoo Han, and Juho Kim, "Clock Scheduling and Cell Library Information Utilization for Power Supply Noise Reduction", in Journal of Semiconductor Technology and Science, Mar. 2009
  • Yooseong Kim, Sangwoo Han, and Juho Kim, "Power Supply Noise Reduction by Clock Scheduling with Gate-Level Current Waveform Estimation", in Proceedings of 5th International SOC Design Conference, Busan, Korea, Nov. 2008 (Best Paper Award)
  • Sangwoo Han, Yooseong Kim, Woosick Choi, Inho Shin, and Youngdoo Choi, "A Second-Order Gate Delay Modeling Method with an Efficient Sensitivity Analysis", in Proceedings of 9th Asia Pacific Conference on Circuits and Systems, Macau, China, Nov. 2008

Teaching Assistant

  • CSE230 Computer Organization and Assembly Language
  • CSE180 Computer Literacy
  • CSE420 Computer Architecture I
  • CSE522 Real-time Embedded Systems


  • CSE598 Topic: Computer Architecture I
  • CSE598 Topic: Compiler Construction I
  • CSE591 Topic: Low Power Computing
  • CSE550 Combinatorial Algorithms and Intractability
  • CSE509 Digital Video Processing
  • CSE598 Topic: Introduction to High Performance Computing
  • CSE531 Distributed Multiprocessor Operating Systems