Updates

• CODES+ISSS Embedded Tutorial: Compilation Techniques for CGRAs: Exploring all parallelization approaches slides - Scott Mahlke, Bjorn de Sutter, Aviral Shrivastava, and Frank Hannig.

About CODES+ISSS

The International Conference on Hardware-Software Codesign and System Synthesis is the premier event in design of embedded systems hardware, software and tools. The conference proudly continues the tradition of being a high-quality forum for active discussion on current and innovative topics. The program will bring together the latest in academic and industrial research and development. High-quality original papers will be accepted for oral presentation followed by interactive poster sessions. Selected papers from the conference proceedings will be targeted for journal publication.

CODES+ISSS 2010 is part of the Embedded Systems Week 2010.

Areas of Interest

The Conference invites papers on all aspects of the design and architecture of embedded computing systems, from application specific to heterogeneous systems, from custom to FPGA implementations, from handheld to high-performance systems. Topics of interest include, but are not limited to:

• High-level, architectural and system-level synthesis - Specification and refinement, design representation, synthesis, partitioning, estimation, design space exploration.
• Hardware-software co-design - Co-design methodologies, interaction between architecture and software design, HW/SW partitioning, design space exploration, HW/SW interface.
• Specification languages and models - System-level models and semantics, timing analysis, power, formal properties, heterogeneous systems and components.
• Simulation and verification - Hardware-software cosimulation, verification methodology, formal verification, HW acceleration, test methodology, design for testability.
• Power-aware design methodology - Power and performance modeling, analysis and estimation techniques, power management approaches, low-power design methodologies.
• Embedded systems architecture - Architecture optimization, application-specific architectures, memory and communication architecture exploration, architecture optimization.
• Embedded software - Compilers, memory management, virtual machines, scheduling, power-aware OS, real-time support and middleware. Multicore and multiprocessor programming models for SoCs and NoCs, profiling techniques and trace generation.
• Multiprocessors and MPSoC -Multiprocessor architectures, design space exploration, MPSoC.
• Network-on-chip - On-chip communication architectures and protocols, switching, routers and communications space exploration.
• Industrial practices and case studies and emerging techniques - Design experiences of high interest to the community. Applications of new state-of-the-art methodologies and tools to real-life problems in various application areas: e.g. wireless, networking, multimedia, automotive, medical systems and sensor networks. New challenges for next generation embedded computing systems, arising from increased heterogeneity, new technologies or new applications.
• Application-specific architectures and algorithms - Application-specific processor architectures and tools, Hardware accelerators and/or processors for network, media and security applications. Reconfigurable processors.

Submission Information

• Papers should represent original work, not published or submitted for publication in other forums.
• A blind review process will be enforced, thus AUTHORS SHOULD NOT REVEAL AUTHORSHIP DIRECTLY OR INDIRECTLY THROUGH REFERENCES.
• Papers must be in PDF format and should not exceed 10 pages in ACM two-column format (9pt on 8.5"x11" letter size paper). For formatting instructions and templates, visit the ACM web site.
• Formal proceedings will be published on CD-ROM and web page forms (copyright by ACM and IEEE).

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