Aviral Shrivastava: Teaching: CSE 420
CSE 420: Computer Architecture I
Catalogue Description
Computer architecture. Performance versus cost tradeoffs. Instruction
set design. Basic processor implementation and pipelining.
Prerequisites
Computer Systems Engineering or Computer Science students and must
have received a C or greater in CSE 230, CSE 330 or EEE 230 or
currently enrolled in CSE 230 or EEE 230.
Course Abstract
"It (Computer Architecture) is not a deary science of paper
machines that will never work. No! It's a discipline of keen
intellectual interest, requiring balance of marketplace forces to
cost-performance-power, leading to glorious failures and some notable
successes." - Hennessy and Patterson.
This course will start with bridging the gap between the high-level
programming languages (e.g. C/C++, Java, perl. python) that we so
conveniently use, and the low-level electronic components
(e.g. transistors, AND gate, OR gate, multiplexors).
This Computer Architecture course then delves into details of
designing a processor. The class is divided into 4 modules, i) A
simple processor design, ii) Pipelining and ILP, iii) Memory
Organization iv) Multi-core processors. Starting from a simple design,
we will strive to make it better. We will learn several fundamental
techniques, like pipelining, caching, and parallel execution, which
enable the modern computing-based world. Although this course takes
the MIPS architecture as a vehicle to explain the complexities and
trade-offs in computer architecture, the concepts are applicable in a
much broader scope. We will take a hands-on approach to understanding
computer architecture. We'll develop simulators to model and thereby
understand computer architecture.
Textbooks
Computer Architecture - A Quantitative Approach 4th Edition
Authors - John L. Hennessey and David A. Patterson
Publisher - Morgan Kaufman, now Elsevier
ISBN: 978-0-12-370490-0
Computer Organization and Design, The Hardware/Software Interface, 4th Edition
Authors - David A. Patterson and John L. Hennessey
Publisher - Morgan Kaufman, now Elsevier
ISBN: 978-0-12-374493-7
Course Contents
- Motivation of this Course
- Introduction to Assembly Language
- Simple Processor Implementation
- Pipelining
- Data Hazards and Register Forwarding
- Control Hazards and Branch Prediction
- Dynamic Scheduling: Register Scoreboarding
- Dynamic Scheduling: Tomasulo's Algorithm
- Memory Hierarchy: Caches
- Memory Hierarchy: Virtual Memory and TLBs
- Multithreading and Multi-cores
- Programming on the 9-core Cell Processor
Course Structure
- Classroom: Lectures will be fast paced,and may cover stuff not
in the text book. Thus I strongly recommend to attend all the lectures
and that you scan the sections before coming to the class, and follow
up after the class.
- Practice Problems: There are practice problems in the
textbook. You are encouraged to do them. You do not have to submit
them for grading.
- Quizzes: You will be tested on the lecture material primarily
through in-class, 45 min, scheduled quizzes. Expect a quiz every
fourth lecture. There will be 5-7 quizzes and the quiz with the lowest
score will be dropped. No alternative test arrangements can be
made.
- Projects: 4-5 programming projects will be given in the course,
in increasing level of difficulty. A lot of programming will be
involved in the course. Depending on the project, you may have the
flexibility of programming in any language that you want. In addition,
dependeing on the project, you are also encouraged to propose your own
project, and you will be awarded "extra grade points" for that. You
have to inform me of the extra work before finishing the project, and
I will decide how much "extra marks" you can get for the extra work.
- Midterm and Final: There will be one midterm and one
Final. Both will be one-hour long, and in the same format as the
quizzes.
- Reading Material: Some interesting and optional reading
material may be provided for the inquisitive. You will not be graded
on it.
Grading Policy
- Quiz(25%): 5-7 quizzes tentatively. Quiz with the lowest score
will be automatically dropped. No other arrangement can be
made. Periodically check course schedule.
- Projects(40%): 4-5 Projects
- Midterm(15%): 1 Midterm
- Final (20%): 1 Final
Last Updated: Aviral Shrivastava, 11/2009