COMPUTER ARCHITECTURE I

Instructor: Dr. Yinong Chen
Office: GWC 228
E-mail: ychen10@imap1.asu.edu
Telephone: 965-2769
Office Hours: T,Th 10:30 - 12:30

Teaching Assistant : Srinivas Rao
Office: GWC 367
E-mail: Srinivas.Rao@asu.edu
Telephone: 965-27-97
Office Hours: M,W 11:00-12:00

1 Introduction
Course Objectives

The objectives of the course are

to understand how different kinds of computers are organized;

to understand instruction set architecture and all aspects of instruction execution in high-performance processors, including pipelining, dynamic scheduling, optimizations in cache design;

to be able to evaluate the design trade-offs;

to be able to represent the increasing importance of I/O in today's computers.

Lecture

T,Th 3:15 - 4:30 PS F101

Textbook

J. L. Hennessy and D. A. Patterson, Computer Architecture-A Quantitative Approach, Morgan Kaufmann, Second Edition, 1995.

References

1. Kai Hwang, Advanced Computer Architecture, McGraw Hill, 1993.

2. Kai Hwang and Zhiwei Xu, Scalable Parallel Computing, McGraw Hill, 1998.

3. Dezso Sima et al., Advanced Computer Architectures, Addison-Wesley, 1997.

Prerequisite

CSE330 Computer Organization and Architecture, or equivalent. Textbook: DA Patterson and JL Hennessy, Computer Organization & Design: The Hardware/Software Interface, Morgen Kaufmann, 2^nd ed. 1998

It is assumed that you are familiar with the following material:

High-level languages and data structures, Programming in C and/or C++, Assembly language programming: opcodes, operands, etc. Logic design, Basic operating system organization. Compiler knowledge will be helpful.

2 Course Description and Tentative Schedule

The material in this course is primarily from textbook and reference #1. The individual topics that will be covered during this semester include the following. Note, the instructor reserves the right to modify course topics and /or schedule, as circumstances require.

Course Overview

Jan 16, 2001.

Quiz1
1 Fundamentals of Computer Design

The Task of the Computer Designer, Technology and Computer Usage Trends, Cost and Trends in Cost, Measuring Performance, Quantitative Principles of Computer Design.

Jan 18, 23, 25 (1.5 weeks)

HW1, Quiz2.
2 Instruction Set Principles and Examples

Classifying Instruction Set Architectures, Memory Addressing, Operations in the Instruction Set, Type and Size of Operands, Encoding an Instruction Set, Role of Compilers

Jan 30, Feb 1, 6, 8, 13, 15 (3 Weeks)

HW2, Quiz3.
3 Pipelining

The Basic Pipeline for DLX, Pipeline Hazards, Data Hazards, Control Hazards, Multi-cycle Operations, exceptions

Feb 20, 22, 27, March 1 (2 Weeks)

Quiz4, project starts.

Mid-Term Exam , March 6, 2000 - 3.15-4.30 p.m.
4 Advanced Pipelining and Instruction Level Parallelism

Instruction Level Parallelism Concepts, Overcoming Data Hazards with Dynamic Scheduling, Branch Prediction, Software, Hardware Support for Exploiting ILP, Studies in ILP

March 8, (midterm break), March 20, 22, 29, April 3, 5, 10 (4 Weeks)

HW3, Quiz5, Quiz6
5 Memory-Hierarchy Design

Caches, Cache Performance, Reducing Cache Misses, Reducing Cache Miss Penalty, Reducing Hit Time, Main Memory, Virtual Memory, Issues in the Design of Memory Hierarchies, -

April 12, 17, 19 (1.5 Weeks)

HW4, Quiz7
6 Storage and I/O Systems

Types of Storage Devices, Buses, I/O Performance Measures, Memory Interface, Designing an I/O System, I/O Benchmarks

April 24, 26, May 1 (1.5 Weeks)

Project due on April 24.
3 Grading

Grades are based on the following components, subject to writing both exams and completing the required project.

Component	Percentage
Mid-Term Exam: March 6,2000 - 3.15-4.30 p.m.	20%
Final Exam (Date to be announced)	50%
Project	10%
Homework	10%
Quizzes	10%

Exams

Both exams will be closed book exams. Missing an exam will receive a grade of E for the course.

Project

The project is an important part of the course. It gives additional experience with the concepts learned in the lecture. Any student who completes only one half or less of the project will receive a grade of E for the course.

Homework

Four homework assignments will be given throughout the semester. Two questions will be picked randomly from each homework set to be graded. To be eligible for credit, each assignment must complete all questions and fulfill the published requirements. Homework should be turned in at the beginning of class on the day it is due. Late assignments will not be accepted.

Quizzes

Quizzes will not be announced. Any quiz that is missed will receive a score of zero -- no exceptions. However, only five of the seven quiz scores will be counted, that is, the lowest two quiz scores will be ignored at the end of the semester.

Notes

Any extenuating circumstances that have an impact on your participation in the course should be discussed with your instructor as soon as those circumstances are known.

An alternative to the graded activity, except quizzes, may be arranged if a student's absence is caused by documented illness or personal emergency. A written explanation (including supporting documentation) must be submitted to your instructor.

The Department of Computer Science and Engineering expects all students to adhere to ASU's policy on Academic Dishonesty. These policies can be found in the Code of Student Conduct:

http://www.asu.edu/aad/manuals/sta/sta104-01.html

Homework and project submitted for evaluation must be your own work. You are encouraged to discuss the assignment with your instructor, your teaching assistant, and your fellow students. However, any part of the work you submit for grading should not be a duplicate of another student's work. The instructor and the teaching assistant will carefully check any possible proliferation.