Bio
Chaitali Chakrabarti received her B. Tech. in Electronics and Electrical Communication Engineering from the Indian Institute of Technology, Kharagpur, India in 1984. She received her M.S. and Ph.D. in Electrical Engineering Dept from U. of Maryland, College Park in 1986 and 1990 respectively. She has been at ASU since fall 1990.
Chaitali's research interests are in the areas of VLSI architectures for signal processing and communications, algorithm-architecture co-design of signal processing systems, and all aspects of low power embedded system design including those that operate at near-threshold voltages. She received Best Paper Awards at SiPS'05 for "A Comprehensive Energy Model and Energy-Quality Evaluation of Wireless Transceiver Front-ends," at SAMOS'07 for "The Next Generation Challenge for Software Defined Radio," at MICRO'08 for "From SODA to Scotch: The Evolution of a Wireless Baseband Processor," at SiPS'10 for "A New Parallel Implementation for Particle Filters and its Application to Adaptive Waveform Design," at HPCA'13 for "Sonic Millip3De: A Massively Parallel 3D-Stacked Accelerator for 3D Ultrasound", at SiPS'16 for "Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low Power Vision Applications" and at SiPS'18 for "Parallel Wavelet-based Bayesian Compressive Sensing based on Gibbs Sampling". Chaitali is an Associate Director of WISCA and a member of SenSIP . She is an Associate Editor of the Journal of VLSI Signal Processing Systems (1999-present), and on the Senior Editorial Board of IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2013-present). She also served as the Associate Editor of IEEE Trans on Signal Processing (1999-2005), IEEE Transactions on VLSI Systems (2007-2013), IEEE Transactions on Multi-scale Computing Systems (2017-2018), and as the Chair of the Technical Committee on Design and Implementation of Signal Processing Systems, IEEE Signal Processing Society, (2006-2007).
Chaitali teaches undergraduate courses on Digital Design Fundamentals, Signals and Systems, Digital Systems and Circuits as well as graduate courses on VLSI Design, and VLSI architectures. She is the recipient of the 1994 CEAS Young Faculty Teaching Excellence award, the 2001 IEEE Phoenix Chapter's Outstanding Educator award, the Top Five Percent Teaching award at the Ira A. Fulton Schools of Engineering Award in 2012, 2014, 2018, 2019, 2020, 2022 and 2023, and the Ira A. Fulton Schools of Engineering Exemplar Faculty Award in 2014 and 2015. Chaitali received the 2013 Distinguished ECE Alumni Award from the ECE Department at the University of Maryland, College Park and the 2018 Distinguished Alumnus Award from the Indian Institute of Technology, Kharagpur. She is also the recipient of the Joseph Palais Distinguished Faculty Scholar Award in 2021. Chaitali is a Fellow of the IEEE.
Research Interests:
Low Power System Design
- Software Defined Radio
- Low Power Algorithm Design
- System-level Design of Emerging Memory Technologiesn
- Reliable Memory System Design
- Memory Design and Exploration
- Energy-Efficient Compilation
- Energy-Efficient Task Scheduling
- Fuel Cell-Battery Hybrid System
- Thermal-aware System Design
- High Level Synthesis for Low Power
VLSI Implementations of Signal Processing and Communication Systems
- Algorithms and Architectures for Portable Ultrasound
- Efficient Implementation of Neural Network Architectures
- Algorithms and Architectures for Speech processing
- Automated Framework for Designing Signal Processing Systems
- Architectures for Efficient Transform Computation
- Algorithms and Architectures for Statistical Signal Processing
- Architectures for Image Processing
- Architectures for Communication Applications
- Algorithms and Architectures for Motion Estimation
Publications:
Here are online versions of publications (93- ).