Chaitali Chakrabarti received her B. Tech. in Electronics and Electrical
Communication Engineering from the Indian Institute of Technology,
Kharagpur, India in 1984. She received her M.S. and Ph.D. in
Electrical Engineering Dept
from
U. of Maryland, College Park in 1986 and 1990 respectively.
She has been at ASU since fall 1990.
Chaitali's research interests are in the areas
of VLSI architectures for
signal processing, communications, and bio-informatic
applications, algorithm-architecture
co-design of signal processing systems,
low power system design
including memory design, compilation issues,
and high level synthesis, CAD tools for VLSI, and
VLSI design. She is a member of the
Consortium for
Embedded Systems and
SenSIP .
She is an Associate Editor of the
Journal of VLSI Signal Processing Systems (1999-present) and
the IEEE Transactions on VLSI Systems (2007-present). She also
served as the Associate Editor of IEEE Trans on Signal Processing
(1999-2005) and as
the Chair of the Technical Committee on
Design and Implementation
of Signal Processing Systems , IEEE Signal Processing Society,
(2006-2007).
She has served on the Program Committees of
ICASSP 1999, ISCAS 2002, ISLPED 01-08,
ISLPED 08,
DAC 2002, DAC 2003, DAC 2004,
SiPS 1996-2008,
SiPS 2008.
Chaitali teaches undergraduate courses on Digital Design Fundamentals,
Signals and Systems, Basic Circuits,
Digital Systems and Circuits as well as the
graduate courses on VLSI Design, and VLSI
architectures. She is the recepient of the
1994 CEAS Young Faculty Teaching
Excellence award, and the 2001 IEEE
Phoenix Chapter's Outstanding
Educator award.
Bio
Research Interests:
Low Power System Design
VLSI Implementations of Signal Processing and Communication Systems
Publications:
Here are online versions of
recent publications (93- ).
Courses: