Chaitali Chakrabarti
Professor

School of Electrical, Computer and Energy Engg.,
Ira A. Fulton Schools of Engineering

Arizona State University, Tempe Arizona 85287-5706
Phone: (480) 965-9516, Fax: (480) 965-8325, Email: chaitali@asu.edu


Research Areas

Research Areas

Low Power System Design

VLSI Implementations of Signal Processing and Communication Systems

Low Power Systems

Software Defined Radio

Mobile devices in the near future are expected to enable users to connect to information ubiquitously from around the world. One of the key challenges in realizing this is the seamless integration and utilization of multiple existing and future wireless communication networks. Designing a device with a separate processor for each wireless protocol is not a scalable solution. We advocate the use of software-defined radio (SDR) which promises to deliver a cost-effective andd flexible solution by implementing a wide variety of wireless protocols in software and running them on the same hardware platform. There are two key challenges in designing a SDR processor for mobile communication devices -- meeting the high computational requirements of wireless protocols and operating the device under a stringent power budget. In close collaboration with the SDR team led by Mudge at the University of Michigan, we have designed several generations of low power SDR processors-- SODA (2006), Ardbeg (2008) and SODA-II (2010) for WCDMA 2Mbps and IEEE 802.11n and AnySP (2009) for 4G and H.264. These programmable processors were all based on a wide-SIMD architecture and had additional features that exploited the characteristics of the protocol algorithms.

  • An Ultra Low Power SIMD Processor for Wireless Devices
    M. Woh, S. Seo, C. Chakrabarti, S. Mahlke and T. Mudge.
    Proc. of the Asilomar Conference on Signals, Systems and Computers, Nov 2010.

  • AnySP: Anytime Anywhere Anyway Signal Processing
    M. Woh, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti and K. Flautner.
    IEEE MICRO Top Picks, Jan/Feb 2010.

  • Mobile Supercomputer for the Next Generation Cell Phone
    M. Woh, S. Mahlke, T. Mudge and C. Chakrabarti.
    IEEE Computer, Jan 2010.

  • A Low Power DSP for Wireless Communications
    H. Lee, C. Chakrabarti and T. Mudge.
    IEEE Trans on VLSI Systems, Sep 2010.

  • Architecture-Aware LDPC Code Design for Multi-Processor Software Defined Radio Systems
    Y. Zhu and C. Chakrabarti.
    IEEE Trans on Signal Processing, Sep 2009.

  • AnySP: Anytime Anywhere Anyway Signal Processing
    M. Woh, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti and K. Flautner.
    Proc. of the International Symposium on Computer Architecture, June 2009.

  • > Customizing Wide-SIMD Architectures for H.264
    S. Seo, M. Woh, S. Mahlke, T. Mudge, S. Vijay and C. Chakrabarti.
    Proc. of the Int. Symp. on Systems, Architectures, Modeling and Simulation, July 2009.

  • From SODA to Scotch: The Evolution of a Wireless Baseband Processor
    M. Woh, Y. Lin, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti, R. Bruce, D. Kershaw, A. Reid, M. Wilder and K. Flautner.
    Proc. of the IEEE/ACM International Symposium on Microarchitecture, Nov 2008. Best Paper Award.

  • A Parameterized Dataflow Language Extension for Embedded Streaming Systems
    Y. Lin, Y. Choi, S. Mahlke, T. Mudge and C. Chakrabarti.
    Proc. of the Int. Symp. on Systems, Architectures, Modeling and Simulation, July 2008.

  • SODA: A High-Performance DSP Architecture for Software Defined Radio
    Y. Lin, H. Lee, M. Woh, S. Mahlke, T. Mudge, Y. Harel, C. Chakrabarti and K. Flautner.
    MICRO Top Picks, Jan/Feb 2007.

  • SODA: A Low Power Architecture for Software Radio
    Y. Lin, H. Lee, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti and K. Flautner.
    Proc. of the Int. Symp. on Computer Architecture, June 2006.

  • The Next Generation Challenge for Software Defined Radio
    M. Woh, S. Seo. H. Lee, Y. Lin, S. Mahlke, T. Mudge, C. Chakrabarti and K. Flautner.
    Proc. of the Int. Symp. on Systems, Architectures, Modeling and Simulation, July 2000. Best Paper Award.

  • Reducing Idle Mode Power in Software Defined Radio Terminals
    H. Lee, T. Mudge and C. Chakrabarti.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Oct 2006.

  • Automatic Antenna-Tuning Unit for Software-Defined and Cognitive Radio
    S.-H. Oh, H. Song, J. Aberle, B. Bakkaloglu and C. Chakrabarti.
    Wireless Communications and Mobile Computing Journal, 2007.

  • A Comprehensive Energy Model and Energy-Quality Evaluation for Wireless Transceiver Front-Ends
    Y. Li, B. Bakkaloglu and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp. 90-103, Jan 2007.

  • Design and Analysis of LDPC Decoders for Software Defined Radio
    S. Seo, T. Mudge, Y. Zhu and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2007.

  • Memory Efficient LDPC Code Design for High Throughput Software Defined Radio Systems
    Y. Zhu and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, April 2007.

  • Architecture-Aware LDPC Code Design for Software Defined Radio
    Y. Zhu and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2006.

  • Design and Implementation of Turbo Decoders for Software Defined Radio
    Y. Lin, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner and A. Reid
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2006.

    Low Power Algorithm Design

    In the design of low power systems, power has to be reduced at all levels of the design -- from algorithm to architecture to circuit to logic to technology. However, the largest power savings are obtained at the highest levels, namely, the systems and the algorithm level. An important technique in algorithmic level power reduction is to use the data characteristics to simplify the algorithm (thereby reducing the power consumption). In this project, we apply the data-dependent technique on a large class of algorithms including DCT, IDCT in image processing, and Viterbi decoding, Turbo decoding and Turbo based space-time decoding in communication systems. For instance, while decoding convolutional codes using the Viterbi algorithm, we have shown how significant energy reduction (70-90%) can be achieved by exploiting real-time variation in system characteristics. The proposed approach adaptively approximates the Viterbi decoding by varying the truncation length and pruning threshold of the T-algorithm while employing trace-back memory management according to variations in SNR, code rate and maximum acceptable BER. Similarly, for the Turbo decoder we found that a judicious use of approximations on the log-MAP algorithm can be used to achieve more than 50% energy savings at a BER=10e-5 with less than a 1dB loss in SNR on a general purpose (superscalar) processor. More recently, we have developed energy-efficient video transmission schemes that reduce the front-end energy of wireless devices by controlling physical layer parameters given link layer specifications.

  • Low Energy Motion Estimation via Selective Approximation
    Y. Emre and C. Chakrabarti.
    Proc. of the IEEE Int. Conf. on Application-specific Systems, Architecturesand Processors, Sep 2011.

  • Energy Efficient Video Transmission over a Wireless Link
    Y. Li, M. Reisslein and C. Chakrabarti.
    IEEE Trans on Vehicular Technology, March 2009.

  • Study of Energy and Performance of Space-Time Decoding Systems in Concatenation with Turbo Decoding
    Y. Zhu, L. Li and C. Chakrabarti
    IEEE Transactions on VLSI Systems, Spring 2006.

  • Design and Implementation of Low Energy Turbo Decoders
    J. Kaza and C. Chakrabarti
    IEEE Transactions on VLSI Systems, Sep 2004.

  • An Approach for Adaptively Approximating the Viterbi Algorithm to Reduce Power Consumption while Decoding Convolutional Codes
    R. Henning and C. Chakrabarti
    IEEE Transactions on Signal Processing, May 2004.

  • Low Power Approach for Decoding Convolutional Codes with Adaptive Viterbi Algorithm Approximation
    R. Henning and C. Chakrabarti
    Proc. of International Symposium on Low Power Electronic Design, 2002.

  • Battery-Friendly Design of Signal Processing Algorithms
    P. Raghavan and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, 2003

  • An Approach for Enabling DCT/IDCT Energy Reduction Scalability in MPEG-2 Video Codecs
    R. Henning and C. Chakrabarti
    Proc. of International Conference on Acoustics, Speech and Signal Processing.

  • A Quality-Energy Tradeoff Approach for IDCT Computation in MPEG-2 Video Decoding
    R. Henning and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, 2000.

    Memory Design

    In systems that involve multidimensional streams of signals such as images or video sequences, it has been shown that the majority of the power cost is not due to the datapath or controllers, but due to memory interactions. This implies that with proper design, reduction in the memory related power budget can far exceed the reduction due to voltage scaling and other popular power saving transformations. In the area of memory management for data-dominated applications, we have demonstrated the necessity of including energy in the performance metrics of a memory exploration procedure. The necessity arises from the fact that the variation in the number of processor cycles is quite different from the variation in the energy consumption for different cache configurations. We have also looked at developing architectural and circuit-level strategies to reduce leakage power consumption in direct mapped and set associative caches. More recently we have focused on low power techniques to correct or compensate for errors in memories. One aspect of this work has been on developing energy-efficient error control coding (ECC) techniques for both SRAM and Flash memories. Another aspect has been on developing algorithm-specific techniques that have very low overhead and perform better than traditional ECC techniques for medium to high error rates.

  • Techniques for Compensating Memory Errors in JPEG2000
    Y. Emre and C. Chakrabarti.
    IEEE Trans on VLSI Systems, Jan 2013.

  • Product Code Schemes for Error Correction in MLC NAND Flash Memories
    C. Yang, Y. Emre and C. Chakrabarti.
    IEEE Trans. on VLSI Systems, Dec 2012.

  • Hierarchical Modeling of Phase Change Memory for Reliable Design
    Z. Xu, K. Sutaria, C. Yang. C. Chakrabarti and Y. Cao.
    Proc. of the Int. Conf. on Computer Design, 2012.

  • Enhancing the Reliability of STT-RAM through Circuit and System-level techniques
    Y. Emre, C. Yang, K. Sutaria, Y. Cao and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2012.

  • A Multi-tiered Approach to Improving the Reliability of Multi-level Cell PRAM
    C. Yang, Y. Emre, Y. Cao and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2012.

  • Flexible Product Code-based ECC Schemes for MLC NAND Flash Memories
    C. Yang. Y. Emre, C. Chakrabarti and T. Mudge Proc. of the IEEE Workshop in Signal Processing Systems, Oct 2011.

  • Memory Error Compensation Techniques for JPEG2000
    Y. Emre and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2010.

  • Energy-aware Error Control Coding for Flash Memories
    V. Papirla and C. Chakrabarti.
    Proc. of the IEEE/ACM Design Automation Conference, July 2008.

  • Memory Subbanking Scheme for High Throughput SISO Decoders
    M. Tiwari, Y. Zhu and C. Chakrabarti
    IEEE Trans on VLSI Systems, April 2005.

  • Multi-port Memory Design for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti.
    Design Automation for Embedded Systems, vol. 9, pp. 235-261, 2005.

  • Memory Design and Exploration for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti.
    Journal of VLSI Signal Processing, pp.167-178, Nov 2001.

  • Data Memory Design and Exploration for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti.
    ACM Transactions on Design and Automation of Electronic Systems, pp. 553-569, Oct 2001.

  • Memory Exploration for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti
    Proc. of the Design Automation Conference, 1999

  • Low Power Multi-module Multi-port Memory Design for Embedded Systems
    W.-T. Shiue, S. Tadas and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, 2000.

  • Architectural Approaches to Reducing Leakage Energy in Caches
    S. Tadas and C. Chakrabarti
    Proc. of International Symposium on Circuits and Systems, 2002.

  • An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits
    H. Rahman and C. Chakrabarti.
    IEEE Trans on Circuits and Systems II, Aug 2005.

    Energy-Efficient Task Scheduling

    In this work we focus on task scheduling algorithms for DVS processor based systems. First we derive algorithms to minimize energy or minimize peak power of the CPU given the task specifications (arrival times, deadline times, execution times, periods) and dependencies. We use the Lagrange multiplier method to theoretically determine the relation between the task voltages such that the energy or power is minimum, and then develop an iterative algorithm that tries to satisfy the relation. We show experimentally (random experiments as well as real-life cases), that the voltage assignment obtained by the proposed low complexity algorithm is very close to that of the optimal energy (0.1\% error) and optimal peak power (1\% error) assignment. Next we design dynamic task scheduling algorithms that minimize the system-level energy (defined by CPU energy + device energy). These algorithms utilize the concepts of optimal scaling factor which minimizes the system-level energy, and dynamic speed setting which is based on processor utilization and remaining workload estimation. We have also developed task scheduling algorithms for battery-operated systems. The important design metric here is maximization of battery lifetime or maximization of battery residual charge. Since the battery lifetime is directly dependent on the battery discharge profile, our approach to lifetime maximization is based on shaping the profile of the load current.

  • Extending the Lifetime of Media Recorders Constrained by Battery and Flash Memory Size
    Y. Kim, Y. Cho, N. Chang, C. Chakrabarti and N. I. Cho.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Aug 2008.

  • Energy-efficient Dynamic Task Scheduling for DVS Systems
    J. Zhuo and C. Chakrabarti.
    ACM Transactions on Embedded Computing Systems, Feb 2008.

  • High-level Power Management of Embedded Systems with Application-Specific Energy Cost Function
    Y. Cho, N. Chang, C. Chakrabarti and S. Vrudhula.
    Proc. of the Design Automation Conference, July 2006.

  • System-Level Energy-Efficient Dynamic Task Scheduling Algorithms
    J. Zhuo and C. Chakrabarti.
    Proc. of the Design Automation Conference (DAC), June 2005.

  • Static Task Scheduling Algorithm for Battery Powered DVS Systems
    P. Chowdhury and C. Chakrabarti.
    IEEE Trans on VLSI Systems, Feb 2005.

  • An Efficient Dynamic Task Scheduling Algorithm for Battery Powered DVS Systems
    J. Zhuo and C. Chakrabarti.
    Proc. of the Asia South Pacific Design Automation Conference (ASP-DAC), Jan 2005.

  • Optimum Buffer Size for Dynamic Voltage Processors
    A. Manzak and C. Chakrabarti
    Proc. of the 14th Int Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)}, Sep 2004.

  • Variable Voltage Task Scheduling Algorithms for Minimizing Energy/Power
    A. Manzak and C. Chakrabarti.
    IEEE Trans on VLSI Systems, April 2003.

  • Battery-Conscious Task Sequencing for Portable Devices including Voltage/Clock Scaling
    D. Rakhmatov, S. Vrudhula and C. Chakrabarti
    Proc. of Design Automation Conference, 2002.

  • Variable Voltage Task Scheduling for Minimizing Energy
    A. Manzak and C. Chakrabarti
    Proc. of International Symposium on Low Power Electronic Design, 2001.

  • Voltage Scaling for Energy Minimization with QoS Constraints
    A. Manzak and C. Chakrabarti
    Proc. of International Conference on Computer Design, 2001.

    Task Scheduling for Fuel Cell-Battery Hybrid Systems

    The energy consumption of many embedded systems used in portable applications has increased significantly in the last decade. As a result, there is a steady demand for a power supply that has higher energy density. Fuel cell (FC) is a viable power source that is clean and has significantly higher energy density compared to batteries. Since FCs cannot follow the rapid change in the power demand of an embedded system, we consider an FC-battery hybrid source in which the FC provides the steady power and the battery follows the variation in the load power. The optimization metric here is minimization of the fuel consumption and not just energy minimization of the embedded system. The optimization framework is utilized to develop FC-aware task scheduling algorithms for embedded systems that consist of DVS and DPM-enabled components.

  • Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids
    J. Zhuo, C. Chakrabarti, K. Lee, N. Chang and S. Vrudhula.
    IEEE Trans on VLSI Systems, Jan 2009.

  • A Fuel Cell-Battery Hybrid for Portable Embedded Systems
    K. Lee, N. Chang, J. Zhuo, C. Chakrabarti, S. Kadri and S. Vrudhula.
    ACM Transactions on Design Automation of Embedded Systems, Jan 2008.

  • Energy Management of DVS-DPM Enabled Embedded Systems Powered by Fuel Cell-Battery Hybrid Source
    J. Zhuo, C. Chakrabarti and N. Chang.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Aug 2007.

  • Dynamic Power Management with Hybrid Power Sources
    J. Zhuo, C. Chakrabarti, K. Lee and N. Chang.
    Proc. of the Design Automation Conference, June 2007.

  • Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids
    J. Zhuo, C. Chakrabarti, N. Chang and S. Vrudhula.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Oct 2006.

  • Extending the LIfetime of Fuel Cell Based Hybrid Systems
    J. Zhuo, C. Chakrabarti, N. Chang and S. Vrudhula.
    Proc. of the Design Automation Conference, July 2006.

    Thermal-Aware Design

  • Throughput of Multi-Core Processors under Thermal Constraints
    R. Rao, S. Vrudhula and C. Chakrabarti.
    Proc. of the Int. Int. Symp. on Low Power Electronics and Design, Aug 2007.

  • An Optimal Analytical Solution for Processor Speed Control with Thermal Constraints
    R. Rao, S. Vrudhula, C. Chakrabarti and N. Chang.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Oct 2006.

    Energy-Efficient Compilation

    An ever-increasing portion of the functionality of today's system is in the form of software. So in order to develop efficient low power systems, it is imperative that the power cost due to the software component be minimized as well. Our aim in this project is to develop compilers that generate low energy machine code without sacrificing performance. We consider processors that support packing (ie., execution of multiple instructions in a single cycle). Our approach is to (i) increase the number of `packed' instructions and (ii) to minimize the number of additional address instructions during address code generation. More recently, we have looked at developing dataflow language extensions for streaming systems such as software defined radio.

  • A Parameterized Dataflow Language Extension for Embedded Streaming Systems
    Y. Lin, Y. Choi, S. Mahlke, T. Mudge and C. Chakrabarti.
    Proc. of the Int. Symp. on Systems, Architectures, Modeling and Simulation, July 2008.

  • Energy-Efficient Address Code Generation for Digital Signal Processors
    S. Udayanarayanan and C. Chakrabarti
    Proc. of Design Automation Conference, 2001

  • Energy-efficient Code Generation for the DSP56K processor
    S. Udayanarayanan and C. Chakrabarti
    Proc. of International Symposium on Low Power Electronic Design, 2000.

  • Instruction-level power model of microcontrollers
    C. Chakrabarti and D. Gaitonde
    Proc. of the International Symposium on Circuits and Systems, 1999

    High Level Synthesis for Low Power

    In scheduling and allocation of the datapath, we have shown how significant power savings can be obtained by using resources that operate at multiple voltages and by exploiting correlation in the data. The latency-constrained, resource-constrained, and latency and resource constrained algorithms that we developed all have polynomial time complexity and produce results comparable to the ones produced by ILP and dynamic programming. In order to exploit the correlation in the data, we have developed a statistical model that relates data characteristics to the transition activity in the nodes of a CMOS circuit. The model is intuitive, easy to use and performs as well as the Dual Bit Type model. We have also demonstrated the effectiveness of this model in guiding scheduling and allocation during high level synthesis of a low power speech codec.

  • A Low Power Scheduling Scheme with Resources Operating at Multiple Voltages
    A. Manzak and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp 6-14, Feb 2002.

  • Low Power Scheduling with Resources Operating at Multiple Voltages
    W.-T. Shiue and C. Chakrabarti.
    IEEE Transactions on Circuits and Systems II, pp. 536-543, June 2000.

  • An Approach to Switching Activity Consideration during High Level Low Power Design Space Exploration
    R. Henning and C. Chakrabarti.
    IEEE Trans on Circuits and Systems II, May 2002.

  • Relating Data Characteristics to Transition Activity in High-level Static CMOS Design
    R. Henning and C. Chakrabarti
    Proc. of VLSI Design 2000

  • A new register allocation scheme for data format converters
    K. Srivatsan, C. Chakrabarti and L. Lucke.
    IEEE Transactions on Circuits and Systems II, pp. 1250-1253, Sep 1999.

  • Scheduling for Minimizing the Number of Memory Accesses in Low Power Applications
    R. Saied and C. Chakrabarti
    Proc. of the VLSI Signal Processing Workshop, 1996

    VLSI Implementations of Signal Processing and Communication Systems

    Automated Framework for Designing Signal Processing Systems

  • Accelerating Neuromorphic Vision Algorithms for Recognition
    A. Al Maashri, M. Debole, M. Cotter, N. Chandramoorthy, Y. Xiao, C. Chakrabarti and V. Narayanan.
    Proc. of Design Automation Conference, June 2012.

  • A Framework for Accelerating Neuromorphic Vision Algorithms on FPGA
    M. debole, A. Al Maashri, M. Cotter, C.-L. Yu, C. Chakrabarti and V. Narayanan.
    Proc. of the International Conference on Computer-Aided Design, Nov 2011.

  • A Hardware Architecture for Accelerating Neuromorphic Vision Algorithms
    A. Al Maashri, M. Debole, C.-L. Yu, C. Chakrabarti and V. Narayanan.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2011.

  • Multi-dimensional DFT IP Generator for FPGA Platforms
    C.-L. Yu, K. Irick, C. Chakrabarti and V. Narayanan IEEE Trans on Circuits and Systems I, April 2011.

  • FPGA Architecture for 2D Discrete Fourier Transform based on 2D Decomposition for Large Sized Data
    C.-L. Yu, J. S. Kim, L. Deng, S. Kestur, V. Narayanan and C. Chakrabarti.
    Journal of Signal Processing Systems, Spring 2011.

  • Accurate Area, Time and Power Models for FPGA-based Implementations
    L. Deng, K. Sobti, Y. Zhang and C. Chakrabarti.
    Journal of Signal Processing Systems, Spring 2010.

  • A Special-purpose Compiler for Look-up Table and Code Generation for Function Evaluation
    Y. Zhang, L. Deng, P. Yedlapalli, S. Muralidharan, H. Zhao. M. Kandemir, C. Chakrabarti, N. Pitsianis and X. Sun.
    Proc. of Design and Test in Europe, March 2010. `i

  • Bandwidth-intensive FPGA Architectures for Multi-dimensional DFT
    C.-L. Yu, C. Chakarabarti, S. Park and V. Narayanan.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, March 2010.

  • An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms using Algorithmic/Architectural Optimization
    J. S. Kim, L. Deng, P. Mangalagiri, K. Irick, K. Sobti, M. Kandemir, V. Narayanan, C. Chakrabarti, N. Pitsianis and X. Sun.
    IEEE Trans on Computers, Dec 2009.

  • FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-Sized Data
    J. S. Kim, C. _L. Yu, L. Deng, S. Kestur, V. Narayanan and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2009.

  • Automated Optimization of Look-Up Table Implemenaations for Function Evaluation on FPGAs
    L. Deng, C. Chakrabarti, N. Pitsianis and X. Sun.
    Proc. of SPIE vol. 8444, Aug 2009.

  • Accurate Models for Estimating Area and Power of FPGA Implementations
    L. Deng, K. Sobti and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, April 2008.

  • TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform
    J. Kim, P. Mangalagiri, K. Irick, M. Kandemir, V. Narayanan, K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis and X. Sun.
    Proc. of the 17th Int. Conf. on Field Programmable Logic and Applications, Aug 2007.

  • Efficient Function Evaluations with Lookup tables for Structured Matrix Operations
    K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, X. Sun, J. Kim, P. Mangalgiri, V. Narayanan and M. Kandemir.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2007.

    Architectures for Efficient Transform Computation

    In this work, we developed specialized architectures for some important transforms, namely, the Discrete Cosine Transform (DCT), the Discrete Hartley Transform (DHT), the Discrete Wavelet Transform (DWT), and more recently, the Discrete Fourier Transform (DFT). We developed systolic array architectures for computing one-dimensional DHT and DCT over N points, when N is factorizable into mutually prime factors. The factorization resulted in the hardware requirements being significantly reduced. Next we, developed a family of optimal architectures with area-time trade-offs for the more general problem of computing any (NxNx ...xN) d-dimensional linear separable transform. In our work on architectures for the DWT, we showed that while the traditional Mallat's algorithm mapped well to a SIMD array of processors and processors with large on-chip memory, new on-line algorithms have to be developed for single chip implementations with limited memory. These on-line algorithms are based on interleaving computations of different octave outputs and allow the algorithm to be folded onto a simple architecture with limited memory, without sacrificing the throughput requirements. We also developed specialized architectures for forward and inverse wavelet transforms using a lifting based scheme for the seven filters proposed in JPEG 2000. Our work on DFT has been on developing architecture-aware algorithm transformations that enable efficient implementation. For instance, we have developed DFT decompositions that take into account the FPGA available resources and the characteristics of off-chip memory access, namely, the burst access pattern of SDRAM memories. The resulting implementation for multidimensional DFT can maintain the maximum memory bandwidth throughout the whole procesure while avoiding matrix transpose operations used in most other existing implementations.

  • A Super-Pipelined Energy Efficient Subthreshold 240MS/s FFT Core in 65nm CMOS
    D. Jeon, M. Seok, C. Chakrabarti, D. Blaauw and D. Sylvester.
    Journal of Solid State Circuits, Jan 2012.

  • Multi-dimensional DFT IP Generator for FPGA Platforms
    C.-L. Yu, K. Irick, C. Chakrabarti and V. Narayanan IEEE Trans on Circuits and Systems I, April 2011.

  • FPGA Architecture for 2D Discrete Fourier Transform based on 2D Decomposition for Large Sized Data
    C.-L. Yu, J. S. Kim, L. Deng, S. Kestur, V. Narayanan and C. Chakrabarti.
    Journal of Signal Processing Systems, Spring 2011.

  • Pipeline Strategy for Improving Optimal Energy Efficiency in Ultra Low Voltage Design
    M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw and D. Sylvester.
    Proc. of the Design Automation Conference, June 2011.

  • A 0.27V, 30MHz, 17.7nJ/transform 1024-pt Complex FFT Core with Super-pipelining
    M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw and D. Sylvester.
    Proc. of the International Solid State Circuits Conference, Feb 2011.

  • Energy-optimized High Performance FFT Processor
    M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw and D. Sylvester.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, June 2011.

  • Bandwidth-intensive FPGA Architectures for Multi-dimensional DFT
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, March 2010.

  • FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-Sized Data
    J. S. Kim, C. _L. Yu, L. Deng, S. Kestur, V. Narayanan and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2009.

  • A Survey of Lifting-Based Discrete Wavelet Transform Architectures
    T. Acharya and C. Chakrabarti.
    Journal of VLSI Signal Processing, March 2006.

  • A VLSI Architecture for Lifting-Based Forward and Inverse Wavelet Transform
    K. Andra, C. Chakrabarti and T. Acharya.
    IEEE Trans on Signal Processing, pp. 966-977, April 2002.

  • Efficient realizations of encoders and decoders based on the 2-D Discrete Wavelet Transform
    C. Chakrabarti and C. Mumford.
    IEEE Transactions on VLSI Systems, pp. 289-298, Sep 1999.

  • A survey of VLSI architectures for Wavelet Transforms
    C. Chakrabarti, M. Vishwanath and R. M. Owens.
    Journal of VLSI Signal Processing}, vol. 14, no. 2, pp. 171-192, Nov 1996.

  • Efficient Realizations of the Discrete and Continuous Wavelet Transforms: from single chip implementations to mappings on SIMD array computers
    C. Chakrabarti and M. Vishwanath.
    IEEE Trans on Signal Processing, pp.759-771, March 1995.

  • A DWT based encoder architecture for symmetrically extended images
    C. Chakrabarti
    Proc. of the International Symposium on Circuits and Systems, 1999

  • Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition
    C. Chakrabarti and J. J\'{a}J\'{a}.
    IEEE Transactions on Computers, pp. 1359-1368, Nov 1990.

  • VLSI architectures for Multidimensional Transforms
    C. Chakrabarti and J. J\'{a}J\'{a}.
    IEEE Transactions on Computers, pp. 1053-1057, Sep 1991.

    Algorithms and Architectures for Statistical Signal Processing

    Our work focuses on efficient implementation of sequential Monte Carlo techniques, such as particle filtering (PF), to estimate state-space parameters in applications such as those in localization and tracking, PF sequentially estimates the states of a dynamic system based on received noisy measurements and is computationally very intensive. We have shown how Sample-Importace-Resampling PF can be parallelized with no loss in algorithm performance thereby enabling PF to be used in real-time tracking. The proposed algorithm has been used to speed up computations in waveform agile sensing and a multiple PF version has been used to efficently track neural activity in brain.

  • Multi-source Neural Activity Estimation and Sensor Scheduling: Algorithms and Hardware Implementation
    L. Miao, S. Michael, N. Kovvali, C. Chakrabarti and A. Papandreou-Suppappola.
    Journal of Signal Processing Systems, (invited paper).

  • Neural Activity Tracking using Spatial Compressive Particle Filtering
    L. Miao, J. J. Zhang, A. Papandreou-Suppappola and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, April 2012.

  • Algorithm and Parallel Implementation of Particle Filtering and its Use in Waveform-Agile Sensing
    L. Miao, J. J. Zhang, C. Chakrabarti and A. Papandreou-Suppappola Journal of Signal Processing Systems, Dec 2011 (invited paper).

  • Real-Time Closed-Loop Tracking of an Unknown Number of Neural Sources using probability Hypothesis Density Particle Filtering
    L. Miao, J. J. Zhang, C. Chakrabarti, A. Papandreou-Suppappola and N. Kovvali.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2011. (Student Best Paper Award Finalist).

  • Multiple Sensor Sequential Tracking of Neural Activity: Algorithm and FPGA Implementation
    L. Miao, J. J. Zhang, C. Chakrabarti and A. Papandreou-Suppappola.
    Proc. of the Asilomar Conference on Signals, Systems and Computers, Nov 2010.

  • A New Parallel Implementation for Particle Filters and its Applications to Adaptive Waveform Design
    L. Miao, J. J. Zhang, C. Chakrabarti and A. Papandreou-Suppappola.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2001. Best Paper Award.

  • Efficient Mapping of Advanced Signal Processing Algorithms on MultiprocessorArchitectures
    B. Manjunath, A. Williams, C. Chakrabarti and A. Papandreou-Suppappola.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2008.

    Architectures for Image Processing

    Our work in this area can be classified into specialized architectures for non-linear filters, Canny edge detector, deblocking filter, color interpolation filters and system-level architectures for JPEG 2000 and H.264/SVC. In our work on architectures for non-linear filters, we showed how the sample rate can be increased by block processing, pipelining in non-recursive sections, applying approximate look ahead techniques to enable pipelining in the recursive sections, and reducing the precision in the data path. Our study included rank order filters such as median filters, morphological filters and weighted order statistic filters. We also looked at algorithm modifications that enable parallelization of computationally-intensive filters such as Canny edge detectors and deblocking filters used in H.264. We developed a comprehensive architecture for JPEG2000 that consists of accelerators for computing the Discrete Wavelet Transform (DWT), Bit Plane Coding (BPC) and Binary Arithmetic Coding (BAC) along with interfacing memories and a global controller. The DWT accelerator implements the transform using a lifting-based scheme. The BPC accelerator operates on the wavelet coefficients, along the bit planes, to generate a context and data bit pair using the EBCOT algorithm. The BAC accelerator then operates on the context and data bit pair using the MQ coder algorithm. Our recent efforts have focused on developing ultra low power image processing systems. We developed a low power, variation-tolerant architecture for color interpolation filtering that is based on a novel design methodology that allows intelligent trade-offs between power, quality and error resiliency. We also developed an ultra low power wide SIMD architecture for digital cameras.

  • Quality-Aware Techniques for Reducing Power of JPEG Codecs
    Y. Emre and C. Chakrabarti.
    Journal of Signal Processing Systems, 69(3), 2012. (invited paper).

  • Transpose-free SAR Imaging on FPGA Platform
    C.-L Yu and C. Chakrabarti.
    Proc. of Int. Symp. on Circuits and Systems, May 2012.

  • Parallel Deblocking Filter for H.264 AVC/SVC
    V. Sundaram and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2010.

  • Diet-SODA: A Power-Efficient Processor for Digital Cameras
    S. Seo, R. Dreslinski, M. Woh, C. Chakrabarti, S. Mahlke and T. Mudge.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Aug 2010.

  • A Distributed Psycho-Visually Motivated Canny Edge Detector
    S. Varadarajan, C. Chakrabarti, L. J. Karam and J. M. Bauza.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, March 2010.

  • An H.264/SVC Memory Architecture Supporting Spatial and Coarse-Grained Quality Scalabilities
    N. Narvekar, B. Konnanath, S. Mehta, S. Chintalapati, J. AlKamal, C. Chakrabarti and L. Karam.
    Proc. of the Int. Conf. on Image Processing, Nov 2009.

  • Design Methodology for Low Power Dissipation and Parametric Robustness through Output Quality Modulation: Application to Color Interpolation Filtering
    N. Banerjee, G. Karkaonstantis, J. H. Choi, C. Chakrabarti and K. Roy.
    IEEE Trans on Computer Aided Design, August 2009.

  • Efficient Image Reconstruction using Partial 2D Fourier Transform
    L. Deng, C.-L. Yu, C. Chakrabarti, J. Kim and V. Narayanan.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2008.

  • Design Methodology to Trade-Off Power, Output Quality and Error Resiliency: Application to Color Interpolation Filtering
    G. Karakonstantis, N. Banerjee, K. Roy and C. Chakrabarti.
    Proc. of the Int. Conf. on Computer Aided Design, Nov 2007.

  • A High Performance JPEG 2000 Architecture
    K. Andra, T. Acharya and C. Chakrabarti
    IEEE Trans on Circuits and Systems for Video Technology, March 2003.

  • Efficient VLSI Implementation of Bit Plane Coder of JPEG2000
    K. Andra, T. Acharya and C. Chakrabarti
    Proc. of SPIE Applications of Digital Image Processing, 2001

  • A Multibit BInary Arithmetic Coding Technique
    K. Andra, T. Acharya and C. Chakrabarti
    Proc. of International Conference on Image Processing, 2000.

  • VLSI Architectures for Weighted Order Statistic Filters
    C. Chakrabarti and L. Lucke.
    Signal Processing, vol.80, pp.1419-1433, 2000.

  • A Digit-Serial Architecture for Gray-Scale Morphological Filtering
    L. E. Lucke and C. Chakrabarti
    IEEE Trans on Image Processing, pp. 387-391, March 95.

  • Novel Sorting Network-Based Architectures for Rank-Order Filters
    C. Chakrabarti and L. Y. Wang.
    IEEE Transactions on VLSI Systems, pp. 502-507, Dec 1994.

  • High Sample Rate Architectures for Median Filters.
    C. Chakrabarti.
    IEEE Trans on Signal Processing, vol. 42, no. 3, pp. 707-712, March 1994.

  • Sorting Network based Architectures for Median Filters
    C. Chakrabarti.
    IEEE Trans on Circuits and Systems}, vol. 40, no. 11, pp.723-727, Nov 1993.

  • A Parallel Programmable Architecture for Linear and Nonlinear Filters
    L. Lucke and C. Chakrabarti.
    1995 IEEE Workshop on on Nonlinear Signal and Image Processing, pp. 891-894, 1995.

    Architectures for Communication Applications

    Our work has been geared towards development of high throughput and low power architectures for Viterbi decoders, Turbo decoders, LDPC decoder and sphere decoders. We have also shown how the decoding algorithms can be parallelized for efficient implementations onto multiprocessor architectures.

  • Parallel High Throughput Soft-Output Sphere Decoding Algorithm
    Q. Qi and C. Chakrabarti.
    Journal of Signal Processing Systems, 68(2), 2012.

  • Parallel High Throughput Soft-Output Sphere Decoder
    Q. Qi and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2010. > Energy-aware OFDM Systems
    Y. Emre and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, March 2010.

  • Architecture-Aware LDPC Code Design for Multi-Processor Software Defined Radio Systems
    Y. Zhu and C. Chakrabarti.
    IEEE Trans on Signal Processing, Sep 2009.

  • Sphere Decoding for Multiprocessor Architectures
    Q. Qi and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2007.

  • Design and Analysis of LDPC Decoders for Software Defined Radio
    S. Seo, T. Mudge, Y. Zhu and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2007.

  • Memory Efficient LDPC Code Design for High Throughput Software Defined Radio Systems
    Y. Zhu and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, April 2007.

  • Architecture-Aware LDPC Code Design for Software Defined Radio
    Y. Zhu and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2006.

  • Design and Implementation of Turbo Decoders for Software Defined Radio
    Y. Lin, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner and A. Reid
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2006.

  • SODA: A Low Power Architecture for Software Radio
    Y. Lin, H. Lee, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti and K. Flautner.
    Proc. of the Int. Symp. on Computer Architecture, June 2006.

  • Aggregated Circulant Matrix based LDPC codes
    Y. Zhu and C. Chakrabarti.
    Proceedings of International Conference on Acoustics, Speech and Signal Processing, 2006.

  • Memory Subbanking Schemes for High Throughput MAP based SISO Decoders
    M. Tiwari, Y. Zhu and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp, 494-498, April 2005.

  • Design and Implementation of Low Energy Turbo Decoders
    J. Kaza and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp. 968-977, Sep 2004.

  • An Approach for Adaptively Approximating the Viterbi Algorithm to Reduce Power Consumption while Decoding Convolutional Codes
    R. Henning and C. Chakrabarti.
    IEEE Transactions on Signal Processing, pp. 1443-1451, May 2004.

  • A New Architecture for the Viterbi Decoder for Code Rate k/n
    H. Li and C. Chakrabarti.
    IEEE Trans on Communications, pp. 158-164, Feb 1996.

    Algorithms and Architectures for Motion Estimation

    In this project our aim was to develop algorithms and architectures for motion estimation, and also to demonstrate that algorithm and architecture development have to occur in an interactive manner for large complex systems. We considered both pixel-domain and feature-domain algorithms. We showed how the same architecture can be used to implement a variety of pixel-domain block matching algorithms, including full-search, 3-step search and 2-level 3-step hierarchical search. This enables the encoder to choose the block matching algorithm that is best suited, given the image characteristics. The large number of computations in these pixel-domain algorithms prompted us to study feature-domain algorithms for motion estimation. We chose to represent the object by straight-line approximations of the boundary using the Hough transform and estimated the motion parameters from shifts in the theta-p space. Both the software and the hardware implementations were successfully tested for a large number of computer generated objects, including those with highly curved boundaries and partially overlapped objects.

  • Hardware Design of a 2-D Motion Estimation System based on the Hough Transform
    H. Li and C. Chakrabarti.
    IEEE Transactions on Circuits and Systems II, vol. 45, no. 1, pp. 80-95, Jan 98.

  • Motion Estimation of 2-Dimensional Objects Based on the Straight Line Hough Transform: A New Approach
    H. Li and C. Chakrabarti.
    Pattern Recognition, vol. 29, no. 8, pp. 1245-1258, Aug 1996.

  • Architectures for Hierarchical and Other Block Matching Algorithms
    G. Gupta and C. Chakrabarti.
    IEEE Transactions on Circuits and Systems for Video Technology, pp. 477-489, Dec 1995.

    Algorithms and Architectures for Portable Ultrasound

  • Reducing the Complexity of Orthogonal Code-based Synthetic Aperture Ultrasound System
    M. Yang, S. Wei and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2012.

  • Design of Orthogonal Coded Excitation for Synthetic Aperture Imaging in Ultrasound Systems
    M. Yang and C. Chakrabarti.
    Proc. of Int. Symp. on Circuits and Systems, May 2012.

    Architectures for Bio-informatic Applications

    Protein structure prediction is one of the core research areas in bio-informatics. This work is on development of specialized architectures to speed up PSIPRED based protein secondary structure prediction algorithm.

  • A Co-processor Architecture for Fast Protein Structure Prediction
    M. Marolia, R. Khoja, T. Acharya and C. Chakrabarti.
    Pattern Recognition, pp. 2494-2505, Dec 2006.


    Chaitali Chakrabarti
    Professor
    chaitali@asu.edu



    Chaitali Chakrabarti
    Last modified: Thu Aug 15 21:04:21 MST 2002