Chaitali Chakrabarti
Professor

School of Electrial, Computer and Energy Engg.,
Ira A. Fulton Schools of Engineering
Arizona State University, Tempe Arizona 85287-5706
Phone: (480) 965-9516, Fax: (480) 965-8325, Email: chaitali@asu.edu

Papers from Chaitali Chakrabarti's group

Contact Chaitali Chakrabarti by email if you have questions or need further information.

1. Multi-dimensional DFT IP Generator for FPGA Platforms
   C.-L. Yu, K. Irick, C. Chakrabarti and V. Narayanan IEEE Trans on Circuits and Systems I, April 2011.

2. FPGA Architecture for 2D Discrete Fourier Transform based on 2D Decomposition for Large Sized Data
   C.-L. Yu, J. S. Kim, L. Deng, S. Kestur, V. Narayanan and C. Chakrabarti.
   Journal of Signal Processing Systems, Spring 2011.

3. Accurate Area, Time and Power Models for FPGA-based Implementations
   L. Deng, K. Sobti, Y. Zhang and C. Chakrabarti.
   Journal of Signal Processing Systems, Sprimg 2010.

4. A Low Power DSP for Wireless Communications
   H. Lee, C. Chakrabarti and T. Mudge.
   IEEE Trans on VLSI Systems, Sep 2010.

5. AnySP: Anytime Anywhere Anyway Signal Processing
   M. Woh, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti and K. Flautner.
   IEEE MICRO Top Picks, Jan/Feb 2010.

6. Mobile Supercomputer for the Next Generation Cell Phone
   M. Woh, S. Mahlke, T. Mudge and C. Chakrabarti.
   IEEE Computer, Jan 2010.

7. Architecture-Aware LDPC Code Design for Multi-Processor Software Defined Radio Systems
   Y. Zhu and C. Chakrabarti.
   IEEE Trans on Signal Processing, Sep 2009.

8. An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms using Algorithmic/Architectural Optimization
   J. S. Kim, L. Deng, P. Mangalagiri, K. Irick, K. Sobti, M. Kandemir, V. Narayanan, C. Chakrabarti, N. Pitsianis and X. Sun.
   IEEE Trans on Computers, Dec 2009.

9. Design Methodology for Low Power Dissipation and Parametric Robustness through Output Quality Modulation: Application to Color Interpolation Filtering
   N. Banerjee, G. Karkaonstantis, J. H. Choi, C. Chakrabarti and K. Roy.
   IEEE Trans on Computer Aided Design, August 2009.

10. Energy Efficient Video Transmission over a Wireless Link
    Y. Li, M. Reisslein and C. Chakrabarti.
    IEEE Trans on Vehicular Technology, March 2009.

11. Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids
    J. Zhuo, C. Chakrabarti, K. Lee, N. Chang and S. Vrudhula.
    IEEE Trans on VLSI Systems, Jan 2009.

12. A Fuel Cell-Battery Hybrid for Portable Embedded Systems
    K. Lee, N. Chang, J. Zhuo, C. Chakrabarti, S. Kadri and S. Vrudhula.
    ACM Transactions on Design Automation of Embedded Systems, Jan 2008.

13. Energy-efficient Dynamic Task Scheduling for DVS Systems
    J. Zhuo and C. Chakrabarti.
    ACM Transactions on Embedded Computing Systems, Feb 2008.

14. SODA: A High-Performance DSP Architecture for Software Defined Radio
    Y. Lin, H. Lee, M. Woh, S. Mahlke, T. Mudge, Y. Harel, C. Chakrabarti and K. Flautner.
    MICRO Top Picks, Jan/Feb 2007.

15. Automatic Antenna-Tuning Unit for Software-Defined and Cognitive Radio
    S.-H. Oh, H. Song, J. Aberle, B. Bakkaloglu and C. Chakrabarti.
    Wireless Communications and Mobile Computing Journal, 2007.

16. A Comprehensive Energy Model and Energy-Quality Evaluation for Wireless Transceiver Front-Ends
    Y. Li, B. Bakkaloglu and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp. 90-103, Jan 2007.

17. Study of Energy and Performance of Space-Time Decoding Systems in Concatenation with Turbo Decoding
    Y. Zhu, L. Li and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pg. 86-90, Jan 2006.

18. A Co-processor Architecture for Fast Protein Structure Prediction
    M. Marolia, R. Khoja, T. Acharya and C. Chakrabarti.
    Pattern Recognition, pp. 2494-2505, Dec 2006.

19. A Survey of Lifting-Based Discrete Wavelet Transform Architectures
    T. Acharya and C. Chakrabarti.
    Journal of VLSI Signal Processing, pp. 321-329, March 2006.

20. An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits
    H. Rahman and C. Chakrabarti.
    IEEE Trans on Circuits and Systems II, August 2005.

21. Memory Subbanking Schemes for High Throughput MAP based SISO Decoders
    M. Tiwari, Y. Zhu and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp, 494-498, April 2005.

22. Static Task Scheduling Algorithm for Battery Powered DVS Systems
    P. Chowdhury and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp. 226-233, Feb 2005.

23. Multi-port Memory Design for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti.
    Design Automation for Embedded Systems, vol. 9, pp. 235-261, 2005.

24. Design and Implementation of Low Energy Turbo Decoders
    J. Kaza and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp. 968-977, Sep 2004.

25. Mobile Supercomputers
    T. Austin, D. Blaauw, S. Mahlke, T. Mudge, C. Chakrabarti and W. Wolf.
    IEEE Computer, pp. 81-83, May 2004.

26. An Approach for Adaptively Approximating the Viterbi Algorithm to Reduce Power Consumption while Decoding Convolutional Codes
    R. Henning and C. Chakrabarti.
    IEEE Transactions on Signal Processing, pp. 1443-1451, May 2004.

27. A High Performance JPEG 2000 Architecture
    K. Andra, C. Chakrabarti and T. Acharya.
    IEEE Trans on Circuits and Systems for Video Technology, pp. 209-218, March 2003.

28. Variable Voltage Task Scheduling Algorithms for Minimizing Energy/Power
    A. Manzak and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp. 270-276, April 2003.

29. An Approach to Switching Activity Consideration during High Level Low Power Design Space Exploration
    R. Henning and C. Chakrabarti.
    IEEE Trans on Circuits and Systems II, pp. 339-351, May 2002.

30. A VLSI Architecture for Lifting-Based Forward and Inverse Wavelet Transform
    K. Andra, C. Chakrabarti and T. Acharya.
    IEEE Trans on Signal Processing, pp. 966-977, April 2002.

31. A Low Power Scheduling Scheme with Resources Operating at Multiple Voltages
    A. Manzak and C. Chakrabarti.
    IEEE Trans on VLSI Systems, pp 6-14, Feb 2002.

32. Memory Design and Exploration for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti.
    Journal of VLSI Signal Processing, pp.167-178, Nov 2001.

33. Data Memory Design and Exploration for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti.
    ACM Transactions on Design and Automation of Electronic Systems, pp. 553-569, Oct 2001.

34. VLSI Architectures for Weighted Order Statistic Filters
    C. Chakrabarti and L. Lucke.
    Signal Processing, vol.80, pp.1419-1433, 2000.

35. Low Power Scheduling with Resources Operating at Multiple Voltages
    W.-T. Shiue and C. Chakrabarti.
    to be published in the IEEE Transactions on Circuits and Systems II, June 2000.

36. Efficient realizations of encoders and decoders based on the 2-D Discrete Wavelet Transform
    C. Chakrabarti and C. Mumford.
    IEEE Transactions on VLSI Systems, pp. 289-298, Sep 1999.

37. A new register allocation scheme for data format converters
    K. Srivatsan, C. Chakrabarti and L. Lucke.
    IEEE Transactions on Circuits and Systems II, pp. 1250-1253, Sep 1999.

38. Hardware Design of a 2-D Motion Estimation System based on the Hough Transform
    H. Li and C. Chakrabarti.
    IEEE Transactions on Circuits and Systems II, vol. 45, no. 1, pp. 80-95, Jan 98.

39. A survey of VLSI architectures for Wavelet Transforms
    C. Chakrabarti, M. Vishwanath and R. M. Owens.
    Journal of VLSI Signal Processing}, vol. 14, no. 2, pp. 171-192, Nov 1996.

40. Motion Estimation of 2-Dimensional Objects Based on the Straight Line Hough Transform: A New Approach
    H. Li and C. Chakrabarti.
    Pattern Recognition, vol. 29, no. 8, pp. 1245-1258, Aug 1996.

41. A New Architecture for the Viterbi Decoder for Code Rate k/n
    H. Li and C. Chakrabarti.
    IEEE Trans on Communications, pp. 158-164, Feb 1996.

42. Architectures for Hierarchical and Other Block Matching Algorithms
    G. Gupta and C. Chakrabarti.
    IEEE Transactions on Circuits and Systems for Video Technology, pp. 477-489, Dec 1995.

43. Efficient Realizations of the Discrete and Continuous Wavelet Transforms: from single chip implementations to mappings on SIMD array computers
    C. Chakrabarti and M. Vishwanath.
    IEEE Trans on Signal Processing, pp.759-771, March 1995.

44. A Digit-Serial Architecture for Gray-Scale Morphological Filtering
    L. E. Lucke and C. Chakrabarti
    IEEE Trans on Image Processing, pp. 387-391, March 95.

45. Novel Sorting Network-Based Architectures for Rank-Order Filters
    C. Chakrabarti and L. Y. Wang.
    IEEE Transactions on VLSI Systems, pp. 502-507, Dec 1994.

46. High Sample Rate Architectures for Median Filters.
    C. Chakrabarti.
    IEEE Trans on Signal Processing, vol. 42, no. 3, pp. 707-712, March 1994.

47. Sorting Network based Architectures for Median Filters
    C. Chakrabarti.
    IEEE Trans on Circuits and Systems}, vol. 40, no. 11, pp.723-727, Nov 1993.

Conference Papers (1994-)

1. Multiple Sensor Sequential Tracking of Neural Activity: Algorithm and FPGA Implementation
   L. Miao, J. J. Zhang, C. Chakrabarti and A. Papandreou-Suppappola.
   Proc. of the Asilomar Conference on Signals, Systems and Computers, Nov 2010.

2. An Ultra Low Power SIMP Processor for Wireless Devices
   M. Woh, S. Seo, C. Chakrabarti, S. Mahlke and T. Mudge.
   Proc. of the Asilomar Conference on Signals, Systems and Computers, Nov 2010.

3. A New Parallel Implementation for Particle Filters and its Applications to Adaptive Waveform Design
   L. Miao, J. J. Zhang, C. Chakrabarti and A. Papandreou-Suppappola.
   Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2001. Best Paper Award.

4. Memory Error Compensation Techniques for JPEG2000
   Y. Emre and C. Chakrabarti.
   Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2010.

5. Parallel Deblocking Filter for H.264 AVC/SVC
   V. Sundaram and C. Chakrabarti.
   Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2010.

6. Parallel High Throughput Soft-Output Sphere Decoder
   Q. Qi and C. Chakrabarti.
   Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2010.

7. Diet-SODA: A Power-Efficient Processor for Digital Cameras
   S. Seo, R. Dreslinski, M. Woh, C. Chakrabarti, S. Mahlke and T. Mudge.
   Proc. of the Int. Symp. on Low Power Electronics and Design, Aug 2010.

8. Energy-aware OFDM Systems
   Y. Emre and C. Chakrabarti.
   Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, March 2010.

9. Bandwidth-intensive FPGA Architectures for Multi-dimensional DFT
   C.-L. Yu, C. Chakarabarti, S. Park and V. Narayanan.
   Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, March 2010.

10. A Distributed Psycho-Visually Motivated Canny Edge Detector
    S. Varadarajan, C. Chakrabarti, L. J. Karam and J. M. Bauza.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, March 2010.

11. A Special-purpose Compiler for Look-up Table and Code Generation for Function Evaluation
    Y. Zhang, L. Deng, P. Yedlapalli, S. Muralidharan, H. Zhao. M. Kandemir, C. Chakrabarti, N. Pitsianis and X. Sun.
    Proc. of Design and Test in Europe, March 2010.

12. An H.264/SVC Memory Architecture Supporting Spatial and Coarse-Grained Quality Scalabilities
    N. Narvekar, B. Konnanath, S. Mehta, S. Chintalapati, J. AlKamal, C. Chakrabarti and L. Karam.
    Proc. of the Int. Conf. on Image Processing, Nov 2009.

13. FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-Sized Data
    J. S. Kim, C. _L. Yu, L. Deng, S. Kestur, V. Narayanan and C. Chakrabarti.
    Proc. of the IEEE Workshop on Signal Processing Systems, Oct 2009.

14. Automated Optimization of Look-Up Table Implemenaations for Function Evaluation on FPGAs
    L. Deng, C. Chakrabarti, N. Pitsianis and X. Sun.
    Proc. of SPIE vol. 8444, Aug 2009.

15. Low Power Robust Signal Processing
    V. Papirla, A. Jain and C. Chakrabarti.
    Proc. of the Int. Symp. on Low Power Electronics and Design, July 2009.

16. Energy-aware Error Control Coding for Flash Memories
    V. Papirla and C. Chakrabarti.
    Proc. of the IEEE/ACM Design Automation Conference, July 2009.

17. AnySP: Anytime Anywhere Anyway Signal Processing
    M. Woh, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti and K. Flautner.
    Proc. of the International Symposium on Computer Architecture, June 2009.

18. From SODA to Scotch: The Evolution of a Wireless Baseband Processor
    M. Woh, Y. Lin, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti, R. Bruce, D. Kershaw, A. Reid, M. Wilder and K. Flautner.
    Proc. of the IEEE/ACM International Symposium on Microarchitecture, Nov 2008. Best Paper Award.

19. Efficient Mapping of Advanced Signal Processing Algorithms on Multiprocessor Architectures
    B. Manjunath, A. Williams, C. Chakrabarti and A. Papandreou-Suppappola.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2008.

20. Efficient Image Reconstruction using Partial 2D Fourier Transform
    L. Deng, C.-L. Yu, C. Chakrabarti, J. Kim and V. Narayanan.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2008.

21. Extending the Lifetime of Media Recorders Constrained by Battery and Flash Memory Size
    Y. Kim, Y. Cho, N. Chang, C. Chakrabarti and N. I. Cho.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Aug 2008.

22. A Parameterized Dataflow Language Extension for Embedded Streaming Systems
    Y. Lin, Y. Choi, S. Mahlke, T. Mudge and C. Chakrabarti.
    Proc. of the Int. Symp. on Systems, Architectures, Modeling and Simulation, July 2008.

23. Accurate Models for Estimating Area and Power of FPGA Implementations
    L. Deng, K. Sobti and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, April 2008.

24. Design Methodology to Trade-Off Power, Output Quality and Error Resiliency: Application to Color Interpolation Filtering
    G. Karakonstantis, N. Banerjee, K. Roy and C. Chakrabarti.
    Proc. of the Int. Conf. on Computer Aided Design, Nov 2007.

25. Sphere Decoding for Multiprocessor Architectures
    Q. Qi and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2007.

26. Design and Analysis of LDPC Decoders for Software Defined Radio
    S. Seo, T. Mudge, Y. Zhu and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2007.

27. Efficient Function Evaluations with Lookup tables for Structured Matrix Operations
    K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, X. Sun, J. Kim, P. Mangalgiri, V. Narayanan and M. Kandemir.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2007.

28. Energy Management of DVS-DPM Enabled Embedded Systems Powered by Fuel Cell-Battery Hybrid Source
    J. Zhuo, C. Chakrabarti and N. Chang.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Aug 2007.

29. Throughput of Multi-Core Processors under Thermal Constraints
    R. Rao, S. Vrudhula and C. Chakrabarti.
    Proc. of the Int. Int. Symp. on Low Power Electronics and Design, Aug 2007.

30. TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform
    J. Kim, P. Mangalagiri, K. Irick, M. Kandemir, V. Narayanan, K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis and X. Sun.
    Proc. of the 17th Int. Conf. on Field Programmable Logic and Applications, Aug 2007.

31. The Next Generation Challenge for Software Defined Radio
    M. Woh, S. Seo. H. Lee, Y. Lin, S. Mahlke, T. Mudge, C. Chakrabarti and K. Flautner.
    Proc. of the Int. Symp. on Systems, Architectures, Modeling and Simulation, July 2007. Best Paper Award.

32. Dynamic Power Management with Hybrid Power Sources
    J. Zhuo, C. Chakrabarti, K. Lee and N. Chang.
    Proc. of the Design Automation Conference, June 2007.

33. Memory Efficient LDPC Code Design for High Throughput Software Defined Radio Systems
    Y. Zhu and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, April 2007.

34. Architecture-Aware LDPC Code Design for Software Defined Radio
    Y. Zhu and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2006.

35. Design and Implementation of Turbo Decoders for Software Defined Radio
    Y. Lin, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner and A. Reid
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Oct 2006.

36. Reducing Idle Mode Power in Software Defined Radio Terminals
    H. Lee, T. Mudge and C. Chakrabarti.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Oct 2006.

37. An Optimal Analytical Solution for Processor Speed Control with Thermal Constraints
    R. Rao, S. Vrudhula, C. Chakrabarti and N. Chang.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Oct 2006.

38. Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids
    J. Zhuo, C. Chakrabarti, N. Chang and S. Vrudhula.
    Proc. of the Int. Symp. on Low Power Electronics and Design, Oct 2006.

39. High-level Power Management of Embedded Systems with Application-Specific Energy Cost Function
    Y. Cho, N. Chang, C. Chakrabarti and S. Vrudhula.
    Proc. of the Design Automation Conference, July 2006.

40. Extending the LIfetime of Fuel Cell Based Hybrid Systems
    J. Zhuo, C. Chakrabarti, N. Chang and S. Vrudhula.
    Proc. of the Design Automation Conference, July 2006.

41. SODA: A Low Power Architecture for Software Radio
    Y. Lin, H. Lee, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti and K. Flautner.
    Proc. of the Int. Symp. on Computer Architecture, June 2006.

42. Aggregated Circulant Matrix Based LDPC Codes
    Y. Zhu and C. Chakrabarti.
    Proc. of the Int. Conf. on Acoustics, Speech and Signal Processing, May 2006.

43. A Comprehensive Energy Model and Energy-Quality Trade-offs for Wireless Transceiver Front-Ends
    Y. Li, B. Bakkaloglu and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Nov 2005.

44. Battery Aware Wireless Ad-Hoc Routing Protocol
    Q. Qi and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Nov 2005.

45. A Co-Processor Architecture for fast Protein Structure Prediction
    M. Marolia, R. Khoja, T. Acharya and C. Chakrabarti.
    Proc. of the IEEE Workshop on Design and Implementation of Signal Processing Systems, Nov 2005.

46. System-Level Energy-Efficient Dynamic Task Scheduling Algorithms
    J. Zhuo and C. Chakrabarti.
    Proc. of the Design Automation Conference (DAC), June 2005.

47. An Efficient Dynamic Task Scheduling Algorithm for Battery Powered DVS Systems
    J. Zhuo and C. Chakrabarti.
    Proc. of the Asia South Pacific Design Automation Conference (ASP-DAC), Jan 2005.

48. Optimum Buffer Size for Dynamic Voltage Processors
    A. Manzak and C. Chakrabarti
    Proc. of the 14th Int Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)}, Sep 2004.

49. Packet Transmission Policies for Battery Operated Communication Systems
    Y. Li and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, Oct 2004

50. Memory Subbanking Scheme for High Throughput Turbo Decoders
    M. Tiwari, Y. Zhu and C. Chakrabarti
    Proc. of Int. Conf on Acoustics, Speech and Signal Processing, May 2004.

51. Parametrized SoC Design for Portable Systems
    S. Bhutoria and C. Chakrabarti
    Proc. of Int. Symp. on Circuits and Systems, May 2004.

52. A Dynamic Task Scheduling Algorithm for Battery Powered DVS Systems
    A. Jameel and C. Chakrabarti
    Proc. of Int. Symp. on Circuits and Systems, May 2004.

53. A Leakage Estimation and Reduction Technique for Scaled CMOS Logic Circuits Considering Gate Leakage
    H. Rahman and C. Chakrabarti
    Proc. of Int. Symp. on Circuits and Systems, May 2004.

54. `Energy Efficient Turbo-based Space-Time Coder
    Y. Zhu, L. Li and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, 2003

55. Battery-Friendly Design of Signal Processing Algorithms
    P. Raghavan and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, 2003

56. Battery-aware Task Scheduling for a System-on-a-Chip Using Voltage/Clock Scaling
    P. Chowdhury and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, 2002

57. Low Power Approach for Decoding Convolutional Codes with Adaptive Viterbi Algorithm Approximation
    R. Henning and C. Chakrabarti
    Proc. of International Symposium on Low Power Electronic Design, 2002.

58. Battery-Conscious Task Sequencing for Portable Devices including Voltage/Clock Scaling
    D. Rakhmatov, S. Vrudhula and C. Chakrabarti
    Proc. of Design Automation Conference, 2002.

59. Energy-Efficient Design of Turbo Decoders
    J. Kaza and C. Chakrabarti
    Proc. of International Conference on Acoustics, Speech and Signal Processing, 2002.

60. Architectural Approaches to Reducing Leakage Energy in Caches
    S. Tadas and C. Chakrabarti
    Proc. of International Symposium on Circuits and Systems, 2002.

61. A High Performance JPEG 2000 Architecture
    K. Andra, T. Acharya and C. Chakrabarti
    Proc. of International Symposium on Circuits and Systems, 2002.

62. Voltage Scaling for Energy Minimization with QoS Constraints
    A. Manzak and C. Chakrabarti
    Proc. of International Conference on Computer Design, 2001.

63. Variable Voltage Task Scheduling for Minimizing Energy
    A. Manzak and C. Chakrabarti
    Proc. of International Symposium on Low Power Electronic Design, 2001.

64. Efficient VLSI Implementation of Bit Plane Coder of JPEG2000
    K. Andra, T. Acharya and C. Chakrabarti
    Proc. of SPIE Applications of Digital Image Processing, 2001

65. Energy-Efficient Address Code Generation for Digital Signal Processors
    S. Udayanarayanan and C. Chakrabarti
    Proc. of Design Automation Conference, 2001

66. An Approach for Enabling DCT/IDCT Energy Reduction Scalability in MPEG-2 Video Codecs
    R. Henning and C. Chakrabarti
    Proc. of International Conference on Acoustics, Speech and Signal Processing.

67. An Efficient Implementation of a Set of Lifting Based Wavelet Filters
    K. Andra, C. Chakrabarti and T. Acharya
    Proc. of International Conference on Acoustics, Speech and Signal Processing, 2001.

68. A Multibit BInary Arithmetic Coding Technique
    K. Andra, T. Acharya and C. Chakrabarti
    Proc. of International Conference on Image Processing, 2000.

69. A VLSI Architecture for Lifting Based Wavelet Transform
    K. Andra, C. Chakrabarti and T. Acharya
    Proc. of IEEE Workshop on Signal Processing Systems, 2000.

70. A Quality-Energy Tradeoff Approach for IDCT Computation in MPEG-2 Video Decoding
    R. Henning and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, 2000.

71. Low Power Multi-module Multi-port Memory Design for Embedded Systems
    W.-T. Shiue, S. Tadas and C. Chakrabarti
    Proc. of IEEE Workshop on Signal Processing Systems, 2000.

72. Variable Voltage Task Scheduling for Minimizing Energy or Minimizing Power
    A. Manzak and C. Chakrabarti
    Proc. of International Conference on Acoustics, Speech and Signal Processing, 2000.

73. Energy-efficient Code Generation for the DSP56000 family
    S. Udayanarayanan and C. Chakrabarti
    Proc. of International Symposium on Low Power Electronic Design, 2000.

74. Relating Data Characteristics to Transition Activity in High-level Static CMOS Design
    R. Henning and C. Chakrabarti
    Proc. of VLSI Design 2000

75. ILP-based Scheme for Low Power Scheduling with Resource Binding
    W.-T. Shiue and C. Chakrabarti
    Proc. of the International Symposium on Circuits and Systems, 2000.

76. A Programmable Processor for Cryptography
    S. Raghuram and C. Chakrabarti
    Proc. of the International Symposium on Circuits and Systems, 2000.

77. Memory Exploration for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti
    Proc. of the Design Automation Conference, 1999

78. Instruction-level power model of microcontrollers
    C. Chakrabarti and D. Gaitonde
    Proc. of the International Symposium on Circuits and Systems, 1999

79. A low power scheduling scheme with resources operating at multiple voltages
    A. Manzak and C. Chakrabarti
    Proc. of the International Symposium on Circuits and Systems, 1999

80. Memory Design and Exploration for Low Power Embedded Systems
    W.-T. Shiue and C. Chakrabarti
    Proc. of the Design and Implementation of Signal Processing Systems, 1999

81. A DWT based encoder architecture for symmetrically extended images
    C. Chakrabarti
    Proc. of the International Symposium on Circuits and Systems, 1999

82. Activity Models for use in Low Power, High Level Synthesis
    R. Henning and C. Chakrabarti
    Proc. of the International Conference on Acoustics, Speech and Signal Processing, 1999

83. Low Power Scheduling with Resources Operating at Multiple Voltages
    W.-T. Shiue and C. Chakrabarti
    Proc. of the International Symposium on Circuits and Systems, 1998

84. VLSI Architectures for Weighted Order Statistic Filters
    C. Chakrabarti and L. E. Lucke
    Proc. of the International Symposium on Circuits and Systems, 1998

85. High-Level design Synthesis of a Low Power VLIW Processor for the IS-54 VSELP Speech Encoder
    R. Henning and C. Chakrabarti
    Proc. of the International Conference on Computer Design, 1997

86. Scheduling for Minimizing the Number of Memory Accesses in Low Power Applications
    R. Saied and C. Chakrabarti
    Proc. of the VLSI Signal Processing Workshop, 1996

87. Hardware Implementation of a 2-D Motion Estimation System Based on the Hough Transform
    H. Li and C. Chakrabarti
    Proc. of the International Symposium on Circuits and Systems, 1996

88. Efficient Realizations of Analysis and Synthesis Filters based on the 2-D Discrete Wavelet Transform
    C. Chakrabarti and C. Mumford
    Proc. of the International Conference on Acoustics, Speech, and Signal Processing, 1996

89. Low Power Data Format Converter Design using Sem-Static Register Allocation
    K. Srivatsan, C. Chakrabarti and L. Lucke.
    Proc. of the International Conference on Computer Design, 1995

90. A Parallel Programmable Architecture for Linear and Nonlinear Filters
    L. Lucke and C. Chakrabarti.
    1995 IEEE Workshop on on Nonlinear Signal and Image Processing, pp. 891-894, 1995.

91. A New Viterbi Decoder Design for Code Rate k/n
    H. Li and C. Chakrabarti.
    Proc. of the IEEE International Conference on Acoustics, Speech, and Signal Processing, 1995.

92. Architectures for the Discrete and Continuous Wavelet Transforms
    C. Chakrabarti, M. Vishwanath and R. M. Owens.
    Proc. of the IEEE International Conference on Acoustics, Speech, and Signal Processing, 1995.

93. Efficient Architectures for Hidden Surface Removal
    C. Chakrabarti and L. Lucke.
    Proc. of the First IEEE International Conference on Image Processing, 1995.

94. A Digit-Serial Architecture for Gray-Scale Morphological Filtering
    L. E. Lucke and C. Chakrabarti
    IEEE International Symposium on Circuits and Systems, vol. 4, pp. 207-210, 1994.

95. Novel Sorting Network-Based Architectures for Rank-Order Filters
    C. Chakrabarti and L. Y. Wang.
    IEEE International Symposium on Circuits and Systems, vol. 3, pp. 89-92, 1994.

96. High Sample Rate Architectures for Block Adaptive Filters.
    S. Karkada, C. Chakrabarti and A. Spanias.
    IEEE International Symposium on Circuits and Systems, vol. 4, pp. 131-134, 1994.

97. VLSI Architectures for Hierarchical Block Matching
    G. Gupta and C. Chakrabarti.
    IEEE International Symposium on Circuits and Systems, vol. 4, pp. 215-219, 1994

98. A VLSI Architecture for Real-Time Hierarchical Encoding/Decoding of Video using the Wavelet Transform
    M. Vishwanath and C. Chakrabarti.
    IEEE International Conference on Acoustics, Speech, and Signal Processing, 1994.

Chaitali Chakrabarti
Professor
chaitali@asu.edu